AT89LP51RB2_14 Datasheet, PDF (176/254 Pages) ATMEL Corporation – 8-bit Microcontroller Compatible with 8051 Products

Table 22-1. Instruction Execution Times and Exceptions⁽¹⁾ (Continued)
SETB C
1
6
1
D3
SETB bit
2
6
2
D2
CPL C
1
6
1
B3
CPL bit
2
6
2
B2
ANL C, bit
2
12
2
82
ANL C, bit
2
12
2
B0
ORL C, bit
2
12
2
72
ORL C, /bit
2
12
2
A0
MOV C, bit
2
6
2
A2
MOV bit, C
2
12
2
92
Clock Cycles
Branching
Bytes
Compatibility
Fast
Hex Code
JC rel
2
12
3
40
JNC rel
2
12
3
50
JB bit, rel
3
12
4
20
JNB bit, rel
3
12
4
30
JBC bit, rel
3
12
4
10
JZ rel
2
12
3
60
JNZ rel
2
12
3
70
SJMP rel
2
12
3
80
ACALL addr11
2
12
3
11,31,51,71,91,
B1,D1,F1
LCALL addr16
3
12
4
12
RET
1
12
4
22
RETI
1
12
4
32
AJMP addr11
2
12
3
01,21,41,61,81,
A1,C1,E1
LJMP addr16
3
12
4
02
JMP @A+DPTR
JMP @A+PC⁽²⁾
1
12
2
12
2
73
3
A5 73
CJNE A, direct, rel
3
12
4
B5
CJNE A, #data, rel
3
12
4
B4
CJNE Rn, #data, rel
3
12
4
B8-BF
CJNE @Ri, #data, rel
CJNE A, @R0, rel⁽²⁾
CJNE A, @R1, rel⁽²⁾
3
12
3
18
3
18
4
B6-B7
4
A5 B6
4
A5 B7
DJNZ Rn, rel
2
12
3
D8-DF
DJNZ direct, rel
3
12
4
D5
NOP
1
6
1
00
Notes: 1. A clock cycle is one period of the output of the system clock divider. For Fast mode the divider
defaults to 1, so the clock cycle equals the oscillator period. For Compatibility mode the divider
176 AT89LP51RB2/RC2/IC2 Preliminary
3722A–MICRO–10/11