ATMEGA323L_14 Datasheet, PDF (169/247 Pages) ATMEL Corporation – Non-volatile Program and Data Memories

Scanning RESET
ATmega323(L)
Figure 90. General Port Pin Schematic diagram
See Boundary Scan
description for details
MOS
PULL-
UP
PLD
PUD
OC
OD
PXn
ID
RL
RD
RESET
Q
D
DDXn
C
WD
RESET
Q
D
PORTXn
C
WP
RP
WP: WRITE PORTX
WD: WRITE DDRX
RL: READ PORTX LATCH
RP: READ PORTX PIN
RD: READ DDRX
n: 0-7
PUD: PULL-UP DISABLE
PuD: JTAG PULL-UP DISABLE
OC: JTAG OUTPUT CONTROL
OD: JTAG OUTPUT DATA
ID: JTAG INPUT DATA
When no alternate port function is present, the Input Data – ID corresponds to the PINn
Register value, Output Data corresponds to the PORTn Register, Output Control corre-
sponds to the Data Direction – DDn Register, and the PuLL-up Disable – PLD –
corresponds to logic expression (DDn OR NOT(PORTBn)).
Digital alternate port functions are connected outside the dotted box in Figure 90 to
make the scan chain read the actual pin value. For Analog function, there is a direct
connection from the external pin to the analog circuit, and a scan chain is inserted on
the interface between the digital logic and the analog circuit.
The RESET pin accepts 5V active low logic for standard reset operation. An observe-
only cell as shown in Figure 91 is inserted at the output from the Reset Detector; RST.
Note: The scanned signal is active high, i.e., the RST signal is the inverse of the external
RESET pin.
1457G–AVR–09/03
169