ATMEGA64_14 Datasheet, PDF (168/414 Pages) ATMEL Corporation – High-performance, Low-power Atmel AVR

ATmega64(L)
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to Figure 77 and Figure 78 for an example. The CPOL functionality is summa-
rized below:
Table 70. CPOL Functionality
CPOL
Leading Edge
0
Rising
1
Falling
Trailing Edge
Falling
Rising
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to Figure 77 and Figure 78 for an example. The CPHA func-
tionality is summarized below:
Table 71. CPHA Functionality
CPHA
Leading Edge
0
Sample
1
Setup
Trailing Edge
Setup
Sample
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have
no effect on the slave. The relationship between SCK and the Oscillator Clock frequency f_osc is
shown in Table 72.
Table 72. Relationship Between SCK and the Oscillator Frequency
SPI2X
0
0
0
0
1
1
1
1
SPR1
0
0
1
1
0
0
1
1
SPR0
0
1
0
1
0
1
0
1
SCK Frequency
f_osc/4
f_osc/16
f_osc/64
f_osc/128
f_osc/2
f_osc/8
f_osc/32
f_osc/64
2490R–AVR–02/2013
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