ATXMEGA16E5_14 Datasheet, PDF (16/147 Pages) ATMEL Corporation – 8/16-bit Atmel AVR XMEGA Microcontrollers

9. EDMA – Enhanced DMA Controller
9.1 Features
z The EDMA Controller allows data transfers with minimal CPU intervention
z from data memory to data memory
z from data memory to peripheral
z from peripheral to data memory
z from peripheral to peripheral
z Four peripheral EDMA channels with separate:
z transfer triggers
z interrupt vectors
z addressing modes
z data matching
z Two peripheral channels can be combined to one standard channel with separate:
z transfer triggers
z interrupt vectors
z addressing modes
z data search
z Programmable channel priority
z From 1byte to 128KB of data in a single transaction
z Up to 64K block transfer with repeat
z 1 or 2 bytes burst transfers
z Multiple addressing modes
z Static
z Increment
z Optional reload of source and destination address at the end of each
z Burst
z Block
z Transaction
z Optional Interrupt on end of transaction
z Optional connection to CRC Generator module for CRC on EDMA data
9.2 Overview
The four-channel enhanced direct memory access (EDMA) controller can transfer data between memories and
peripherals, and thus offload these tasks from the CPU. It enables high data transfer rates with minimum CPU
intervention, and frees up CPU time. The four EDMA channels enable up to four independent and parallel transfers.
The EDMA controller can move data between SRAM and peripherals, between SRAM locations and directly between
peripheral registers. With access to all peripherals, the EDMA controller can handle automatic transfer of data to/from
communication modules. The EDMA controller can also read from EEPROM memory.
Data transfers are done in continuous bursts of 1 or 2 bytes. They build block transfers of configurable size from 1 byte to
64KB. Repeat option can be used to repeat once each block transfer for single transactions up to 128KB. Source and
destination addressing can be static or incremental. Automatic reload of source and/or destination addresses can be
done after each burst or block transfer, or when a transaction is complete. Application software, peripherals, and events
can trigger EDMA transfers.
The four EDMA channels have individual configuration and control settings. This includes source, destination, transfer
triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a
transaction is complete or when the EDMA controller detects an error on an EDMA channel.
XMEGA E5 [DATASHEET] 16
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014