AT75C220 Datasheet, PDF (16/144 Pages) ATMEL Corporation – Smart Internet Appliance Processor(SIAP)

External Bus Interface
The external bus interface (EBI) generates the signals
which control access to external memories or peripheral
devices.
SMC: Static Memory Controller
The static memory controller (SMC) is used by the
AT75C220 to access external static memory devices.
Static memory devices include external Flash, SRAM or
peripherals.
The SMC provides a glueless memory interface to external
memory using the common address and data bus and
some dedicated control signals. The SMC is highly pro-
grammable and has up to 24 bits of address bus, a 32- or
16-bit data bus and up to four chip select lines. The SMC
supports different access protocols allowing single clock-
cycle accesses. The SMC is programmed as an internal
peripheral that has a standard APB bus interface and a set
of memory-mapped registers. The SMC shares the exter-
nal address and data buses with the DMC and any external
bus master.
External Memory Mapping
The memory map associates the internal 32-bit address
space with the external 24-bit address bus. The memory
map is defined by programming the base address and
page size of the external memories. Note that A[2:23] is
only significant for 32-bit memory and A[1:23] for 16-bit
memory.
If the physical memory-mapped device is smaller than the
programmed page size, it wraps around and appears to be
repeated within the page. The SMC correctly handles any
valid access to the memory device within the page.
In the event of an access request to an address outside
any programmed page, an abort signal is generated by the
internal decoder. Two types of abort are possible: instruc-
tion prefetch abort and data abort. The corresponding
exception vector addresses are 0x0000000C and
0x00000010. It is up to the system programmer to program
the exception handling routine used in case of an abort.
If the AT75C220 is in internal boot mode, any chip select
configured with a base address of zero will be disabled as
the internal ROM is mapped to address zero.
Table 6. Signal Interface
FPDRAM Description
A[23:0]
Address bus
D[31:0]
Data bus
NCE[3:0] Active low chip enables
NWE[3:0] Active low byte select/write strobe signals
NWR
Active low write strobe signals
NSOE
Active low read enable signal
NWAIT
Active low wait signal
Type
Output
I/O
Output
Output
Output
Output
Input
Notes
D[15:0] used when data bus width is 16
NCE[3] can be configured for LCD interface mode
Data Bus Width
A data bus width of 32 or 16 bits can be selected for each
chip select. This option is controlled by the DBW field in the
Chip Select Register (SMC_CSR) of the corresponding
chip select.
The AT75C220 always boots up with a data bus width of 16
bits set in SMC_CSR0.
Byte-write or Byte-select Mode
Each chip select with a 32-/16-bit data bus operates with
one or two different types of write mode:
1. Byte-write mode supports four (32-bit bus) or two
(16-bit bus) byte writes and a single read signal.
2. Byte-select mode selects the appropriate byte(s)
using four (32-bit bus) or two (16-bit bus) byte-select
lines and separate read and write signals.
This option is controlled by the BAT field in SMC_CSR for
the corresponding chip select.
Byte-write access can be used to connect four 8-bit devices
as a 32-bit memory page or two 8-bit devices as a 16-bit
memory page.
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AT75C220