AT75C220 Datasheet, PDF (130/144 Pages) ATMEL Corporation – Smart Internet Appliance Processor(SIAP)

• PCS: Peripheral Chip Select
This field is only used if fixed peripheral select is active (PS=0).
If PCSDEC=0:
PCS = xxx0 NPCS[3:0] = 1110
PCS = xx01 NPCS[3:0] = 1101
PCS = x011 NPCS[3:0] = 1011
PCS = 0111 NPCS[3:0] = 0111
PCS = 1111 forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC=1:
NPCS[3:0] output signals = PCS
• DLYBCS: Delay Between Chip Selects
This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-
overlapping chip selects and solves bus contentions in case of peripherals with long data float times.
If DLYBCS equals zero, one SPI Master Clock period will be inserted by default.
Otherwise, the following equation determines the delay:
NPCS_to_SPCK_Delay = DLYBCS × SPI_Master_Clock_Period
SPI Receive Data Register
Register Name:SP_RDR
Access Type:Read-only
Reset Value:0x0
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
PCS
15
14
13
12
11
10
9
8
RD
7
6
5
4
3
2
1
0
RD
• RD: Receive Data
Data received by the SPI interface is stored in this register right-justified. Unused bits read zero.
• PCS: Peripheral Chip Select Status
In master mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read
as zero.
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AT75C220