ATTINY87_14 Datasheet, PDF (157/261 Pages) ATMEL Corporation – 8-bit AVR Microcontroller with 8K/16K Bytes In-System

15.5.4 Configuration
Depending on the mode (LIN or UART), LCONF[1..0] bits of the LINCR register set the controller in the following
configuration (see Table 15-3).
Table 15-3. Configuration Table versus Mode
Mode
LCONF[1..0]
00 _b
LIN
01 _b
10 _b
11 _b
00 _b
UART
01 _b
10 _b
11 _b
Configuration
LIN standard configuration (default)
No CRC field detection or transmission
Frame_time_out disable
Listening mode
8-bit data, no parity and 1 stop-bit
8-bit data, even parity and 1 stop-bit
8-bit data, odd parity and 1 stop-bit
Listening mode, 8-bit data, no parity and 1 stop-bit
The LIN configuration is independent of the programmed LIN protocol.
The listening mode connects the internal Tx LIN and the internal Rx LIN together. In this mode, the TXLIN output pin is
disabled and the RXLIN input pin is always enabled. The same scheme is available in UART mode.
Figure 15-6. Listening Mode
internal
Tx LIN
LISTEN
internal
1
Rx LIN
0
TXLIN
RXLIN
15.5.5 Busy Signal
LBUSY bit flag in LINSIR register is the image of the BUSY signal. It is set and cleared by hardware. It signals that the
controller is busy with LIN or UART communication.
15.5.5.1 Busy Signal in LIN Mode
Figure 15-7. Busy Signal in LIN Mode
HEADER
FRAME SLOT
LIN Bus
1) LBUSY
BREAK
Field
SYNC
Field
PROTECTED
IDENTIFIER
Field
Node providing the master task
DATA-0
Field
RESPONSE
DATA-n
Field
CHECKSUM
Field
2) LBUSY
3) LBUSY
Node providing a slave task
Node providing neither the master task, neither a slave task
LCMD = Tx Header
LIDOK
LCMD = Tx or Rx Response
LTXOK or LRXOK
ATtiny87/ATtiny167 [DATASHEET] 157
7728H–AVR–03/14