ATTINY20_14 Datasheet, PDF (153/219 Pages) ATMEL Corporation – 8-bit AVR Microcontroller

All the instructions except the SKEY instruction require the instruction to be followed by one byte operand. The SKEY
instruction requires 8 byte operands. For more information, see the TPI instruction set on page 153.
18.4.2 Exception Handling and Synchronisation
Several situations are considered exceptions from normal operation of the TPI. When the TPI physical layer is in receive
mode, these exceptions are:
z The TPI physical layer detects a parity error.
z The TPI physical layer detects a frame error.
z The TPI physical layer recognizes a BREAK character.
When the TPI physical layer is in transmit mode, the possible exceptions are:
z The TPI physical layer detects a data collision.
All these exceptions are signalized to the TPI access layer. The access layer responds to an exception by aborting any
on-going operation and enters the error state. The access layer will stay in the error state until a BREAK character has
been received, after which it is taken back to its default state. As a consequence, the external programmer can always
synchronize the protocol by simply transmitting two successive BREAK characters.
18.5
Instruction Set
The TPI has a compact instruction set that is used to access the TPI Control and Status Space (CSS) and the data
space. The instructions allow the external programmer to access the TPI, the NVM Controller and the NVM memories. All
instructions except SKEY require one byte operand following the instruction. The SKEY instruction is followed by 8 data
bytes. All instructions are byte-sized.
The TPI instruction set is summarized in Table 18-1.
Table 18-1. Instruction Set Summary
Mnemonic
SLD
SLD
SST
SST
SSTPR
SIN
SOUT
SLDCS
SSTCS
SKEY
Operand
data, PR
data, PR+
PR, data
PR+, data
PR, a
data, a
a, data
data, a
a, data
Key, {8{data}}
Description
Serial LoaD from data space using indirect addressing
Serial LoaD from data space using indirect addressing
and post-increment
Serial STore to data space using indirect addressing
Serial STore to data space using indirect addressing
and post-increment
Operation
data ← DS[PR]
data ← DS[PR]
PR ← PR+1
DS[PR] ← data
DS[PR] ← data
PR ← PR+1
Serial STore to Pointer Register using direct
addressing
Serial IN from data space
Serial OUT to data space
PR[a] ← data
data ← I/O[a]
I/O[a] ← data
Serial LoaD from Control and Status space using direct
addressing
data ← CSS[a]
Serial STore to Control and Status space using direct
addressing
Serial KEY
CSS[a] ← data
Key ← {8{data}}
ATtiny20 [DATASHEET]
Atmel-8235F-AVR-ATtiny20-Datasheet_09/2014
153