ATTINY20_14 Datasheet, PDF (133/219 Pages) ATMEL Corporation – 8-bit AVR Microcontroller

Table 16-4. CPHA Functionality
CPHA
0
1
Leading Edge
Sample
Setup
Trailing Edge
Setup
Sample
z Bits 1:0 – SPR[1:0]: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave.
The relationship between SCK and the I/O clock frequency f_{clk_I/O} is shown in the following table:
Table 16-5. Relationship Between SCK and the I/O Clock Frequency
SPI2X
0
0
0
0
1
1
1
1
SPR1
0
0
1
1
0
0
1
1
SPR0
0
1
0
1
0
1
0
1
SCK Frequency
f_{clk_I/O}/4
f_{clk_I/O}/16
f_{clk_I/O}/64
f_{clk_I/O}/128
f_{clk_I/O}/2
f_{clk_I/O}/8
f_{clk_I/O}/32
f_{clk_I/O}/64
16.5.2 SPSR – SPI Status Register
Bit
0x2F
Read/Write
Initial Value
7
6
5
4
3
2
1
0
SPIF
WCOL
–
–
–
–
–
SPI2X
SPSR
R/W
R/W
R
R
R
R
R
R/W
0
0
0
0
0
0
0
0
z Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global
interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag.
SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is
cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
z Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit)
are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register.
z Bits 5:1 – Res: Reserved Bits
These bits are reserved and will always read as zero.
z Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see
Table 16-5). This means that the minimum SCK period will be two I/O clock periods. When the SPI is configured as
Slave, the SPI is only guaranteed to work at f_{clk_I/O}/4 or lower.
ATtiny20 [DATASHEET]
Atmel-8235F-AVR-ATtiny20-Datasheet_09/2014
133