ATMEGA325PV_14 Datasheet, PDF (151/364 Pages) ATMEL Corporation – High Performance, Low Power AVR

ATmega325P/3250P
• Bit 2:0 – CS22:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table
16-6.
Table 16-6.
CS22
0
0
0
0
1
1
1
1
Clock Select Bit Description
CS21
CS20
Description
0
0
No clock source (Timer/Counter stopped).
0
1
clk_T2S/(No prescaling)
1
0
clk_T2S/8 (From prescaler)
1
1
clk_T2S/32 (From prescaler)
0
0
clk_T2S/64 (From prescaler)
0
1
clk_T2S/128 (From prescaler)
1
0
clk_T2S/256 (From prescaler)
1
1
clk_T2S/1024 (From prescaler)
16.10.2 TCNT2 – Timer/Counter Register
16.10.3
Bit
(0xB2)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
TCNT2[7:0]
TCNT2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a compare match between TCNT2 and the OCR2A Register.
OCR2A – Output Compare Register A
16.10.4
Bit
(0xB3)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
OCR2A[7:0]
OCR2A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC2A pin.
ASSR – Asynchronous Status Register
Bit
7
6
5
4
3
2
1
0
(0xB6)
–
–
–
EXCLK
AS2
TCN2UB OCR2UB TCR2UB
ASSR
Read/Write
R
R
R
R/W
R/W
R
R
R
Initial Value
0
0
0
0
0
0
0
0
8023F–AVR–07/09
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