U3741BM Datasheet, PDF (15/32 Pages) ATMEL Corporation – UHF ASK RECEIVER IC

U3741BM
Figure 13. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max)
(Lim_min = 14, Lim_max = 24)
Bit check failed (CV_Lim = Lim_max)
Enable IC
Bit check
Dem_out
Bit check
Counter
1/2 Bit
0
1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 101112 13141516171819 2021222324
Startup Mode
Bit check Mode
0
Sleep Mode
Duration of the Bit Check
Receiving Mode
Digital Signal Processing
If no transmitter signal is present during the bit check, the output of the ASK/FSK
demodulator delivers random signals. The bit check is a statistical process and T_Bitcheck
varies for each check. Therefore, an average value for T_Bitcheck is given in “Electrical
Characteristics”. T_Bitcheck depends on the selected baud rate range and on T_Clk. A higher
baudrate range causes a lower value for T_Bitcheck resulting in lower current consumption
in polling mode.
In the presence of a valid transmitter signal, T_Bitcheck is dependant on the frequency of
that signal, f_Sig and the count of the checked bits, N_Bitcheck. A higher value for N_Bitcheck
thereby results in a longer period for T_Bitcheck requiring a higher value for the transmitter
preburst T_Preburst.
If the bit check has been successful for all bits specified by N_Bitcheck, the receiver
switches to receiving mode. According to Figure 9 on page 13, the internal data signal is
switched to pin DATA in that case. A connected microcontroller can be woken up by the
negative edge at pin DATA. The receiver stays in that condition until it is switched back
to polling mode explicitly.
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different
ways and as a result converted into the output signal data. This processing depends on
the selected baud rate range (BR_Range). Figure 14 on page 16 illustrates how
Dem_out is synchronized by the extended clock cycle T_XClk. This clock is also used for
the bit check counter. Data can change its state only after T_XClk elapsed. The
edge-to-edge time period t_ee of the Data signal as a result is always an integral multiple
of T_XClk.
The minimum time period between two edges of the data signal is limited to
t_ee ≥ T_{DATA_min}. This implies an efficient suppression of spikes at the DATA output. At the
same time, it limits the maximum frequency of edges at DATA. This eases the interrupt
handling of a connected microcontroller. T_{DATA_min} is to some extent affected by the pre-
ceding edge-to-edge time interval t_ee as illustrated in Figure 15. If t_ee is in between the
specified bit check limits, the following level is frozen for the time period
T_{DATA_min} = tmin1, in case of t_ee being outside that bit check limits T_{DATA_min} = tmin2 is the
relevant stable time period.
The maximum time period for DATA to be low is limited to T_{DATA_L_max}. This function
ensures a finite response time during programming or switching off the receiver via pin
DATA. T_{DATA_L_max} is thereby longer than the maximum time period indicated by the
transmitter data stream. Figure 16 gives an example where Dem_out remains low after
the receiver has switched to receiving mode.
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4662B–RKE–10/04