ATMEGA128A_1 Datasheet, PDF (143/386 Pages) ATMEL Corporation – Write/Erase cycles: 10,000 Flash/100,000 EEPROM

ATmega128A
15.11.19 TIFR - Timer/Counter Interrupt Flag Register
Bit
Read/Write
Initial Value
7
OCF2
R/W
0
6
TOV2
R/W
0
5
ICF1
R/W
0
4
OCF1A
R/W
0
3
OCF1B
R/W
0
2
TOV1
R/W
0
1
OCF0
R/W
0
0
TOV0
R/W
0
TIFR
Note: This register contains flag bits for several Timer/Counters, but only timer 1 bits are described in
this section. The remaining bits are described in their respective timer sections.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register
(ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 flag is set when the coun-
ter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt vector is executed. Alternatively,
ICF1 can be cleared by writing a logic one to its bit location.
• Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register A (OCR1A).
Note that a forced output compare (FOC1A) strobe will not set the OCF1A flag.
OCF1A is automatically cleared when the Output Compare Match A interrupt vector is executed.
Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
• Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register B (OCR1B).
Note that a forced output compare (FOC1B) strobe will not set the OCF1B flag.
OCF1B is automatically cleared when the Output Compare Match B interrupt vector is executed.
Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
• Bit 2 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In normal and CTC modes, the
TOV1 flag is set when the timer overflows. Refer to Table 15-5 on page 136 for the TOV1 flag
behavior when using another WGMn3:0 bit setting.
• TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector is
executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
15.11.20 ETIFR - Extended Timer/Counter Interrupt Flag Register
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
–
–
ICF3
OCF3A OCF3B
TOV3
OCF3C OCF1C
ETIFR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
• Bit 7:6 – Reserved
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be set to zero when ETIFR is written.
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