ATMEGA128A_1 Datasheet, PDF (134/386 Pages) ATMEL Corporation – Write/Erase cycles: 10,000 Flash/100,000 EEPROM

ATmega128A
Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)
clk_I/O
clk_Tn
(clk_I/O/8)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
TOP - 1
TOP - 1
TOP
TOP
Old OCRnx Value
BOTTOM
TOP - 1
BOTTOM + 1
TOP - 2
New OCRnx Value
15.11 Register Description
15.11.1 TCCR1A - Timer/Counter1 Control Register A
Bit
Read/Write
Initial Value
7
COM1A1
R/W
0
6
COM1A0
R/W
0
5
COM1B1
R/W
0
4
COM1B0
R/W
0
3
COM1C1
R/W
0
2
COM1C0
R/W
0
1
WGM11
R/W
0
0
WGM10
R/W
0
TCCR1A
15.11.2 TCCR3A - Timer/Counter3 Control Register A
Bit
Read/Write
Initial Value
7
COM3A1
R/W
0
6
COM3A0
R/W
0
5
COM3B1
R/W
0
4
COM3B0
R/W
0
3
COM3C1
R/W
0
2
COM3C0
R/W
0
1
WGM31
R/W
0
0
WGM30
R/W
0
TCCR3A
• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
• Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C
The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB,
and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the
OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or
both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port func-
tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one,
the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How-
ever, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or
OCnC pin must be set in order to enable the output driver.
When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is
dependent of the WGMn3:0 bits setting. Table 15-2 shows the COMnx1:0 bit functionality when
the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM).
8151G–AVR–07/10
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