ATMEGA8535L_14 Datasheet, PDF (142/321 Pages) ATMEL Corporation – Nonvolatile Program and Data Memories

be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to
re-enable SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero,
SCK is low when idle. Refer to Figure 67 and Figure 68 for an example. The CPOL func-
tionality is summarized below:
Table 57. CPOL Functionality
CPOL
Leading Edge
Trailing Edge
0
Rising
Falling
1
Falling
Rising
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading
(first) or trailing (last) edge of SCK. Refer to Figure 67 and Figure 68 for an example.
The CPOL functionality is summarized below:
Table 58. CPHA Functionality
CPHA
Leading Edge
Trailing Edge
0
Sample
1
Setup
Setup
Sample
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator
Clock frequency f_osc is shown in the following table:
Table 59. Relationship between SCK and the Oscillator Frequency
SPI2X
0
0
0
0
1
1
1
1
SPR1
0
0
1
1
0
0
1
1
SPR0
0
1
0
1
0
1
0
1
SCK Frequency
f_osc/4
f_osc/16
f_osc/64
f_osc/128
f_osc/2
f_osc/8
f_osc/32
f_osc/64
142 ATmega8535(L)
2502K–AVR–10/06