AT83C5136_14 Datasheet, PDF (14/166 Pages) ATMEL Corporation – Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply

In order to optimize the power consumption, the oscillator inverter is inactive when the PLL out-
put is not selected for the USB device.
Figure 6-2. Crystal Connection
C1
C2
VSS
X1
Q
X2
6.3 PLL
6.3.1
PLL Description
The AT83C5134/35/36 PLL is used to generate internal high frequency clock (the USB Clock)
synchronized with an external low-frequency (the Peripheral Clock). The PLL clock is used to
generate the USB interface clock. Figure 6-3 shows the internal structure of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the
comparison between the reference clock coming from the N divider and the reverse clock com-
ing from the R divider and generates some pulses on the Up or Down signal depending on the
edge position of the reverse clock. The PLLEN bit in PLLCON register is used to enable the
clock generation. When the PLL is locked, the bit PLOCK in PLLCON register (see Figure 6-3) is
set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by inject-
ing or extracting charges from the external filter connected on PLLF pin (see Figure 6-4). Value
of the filter components are detailed in the Section “DC Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage V_REF produced by
the charge pump. It generates a square wave signal: the PLL clock.
Figure 6-3. PLL Block Diagram and Symbol
OSC
CLOCK
N divider
N3:0
PLLCON.1
PLLEN
PLLF
Up
PFLD
Vref
CHP
Down
PLOCK
PLLCON.0
R divider
R3:0
VCO
USBclk = -^O-----^S----^C-----c---l--k----^×-----⁽--R------+-----1----⁾
N+1
USB Clock
USB
CLOCK
USB Clock Symbol
14 AT83C5134/35/36
7683C–USB–11/07