ATMEGA88PV-10PU Datasheet, PDF (134/420 Pages) ATMEL Corporation – 8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash

Table 16-4. Waveform Generation Mode Bit Description⁽¹⁾
Mode WGM13
WGM12 WGM11 WGM10 Timer/Counter Mode of
(CTC1) (PWM11) (PWM10) Operation
TOP
Update of TOV1 Flag
OCR1x at Set on
0
0
0
0
0
Normal
0xFFFF Immediate MAX
1
0
0
0
1
PWM, Phase Correct, 8-bit
0x00FF
TOP
BOTTOM
2
0
0
1
0
PWM, Phase Correct, 9-bit
0x01FF
TOP
BOTTOM
3
0
0
1
1
PWM, Phase Correct, 10-bit 0x03FF TOP
BOTTOM
4
0
1
0
0
CTC
OCR1A Immediate MAX
5
0
1
0
1
Fast PWM, 8-bit
0x00FF BOTTOM TOP
6
0
1
1
0
Fast PWM, 9-bit
0x01FF BOTTOM TOP
7
0
1
1
1
Fast PWM, 10-bit
0x03FF BOTTOM TOP
8
1
0
0
0
PWM, Phase and Frequency
Correct
ICR1
BOTTOM BOTTOM
9
1
0
0
1
PWM, Phase and Frequency
Correct
OCR1A
BOTTOM
BOTTOM
10
1
0
1
0
PWM, Phase Correct
ICR1
TOP
BOTTOM
11
1
0
1
1
PWM, Phase Correct
OCR1A TOP
BOTTOM
12
1
1
0
0
CTC
ICR1
Immediate MAX
13
1
1
0
1
(Reserved)
–
–
–
14
1
1
1
0
Fast PWM
ICR1
BOTTOM TOP
15
Note:
1
1
1
1
Fast PWM
OCR1A BOTTOM TOP
1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
16.11.2
TCCR1B – Timer/Counter1 Control Register B
Bit
7
6
5
(0x81)
ICNC1
ICES1
–
Read/Write
R/W
R/W
R
Initial Value
0
0
0
4
WGM13
R/W
0
3
WGM12
R/W
0
2
CS12
R/W
0
1
CS11
R/W
0
0
CS10
R/W
0
TCCR1B
• Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four
successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture
event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the
Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
134 ATmega48P/88P/168P
8025M–AVR–6/11