TH7887A Datasheet, PDF (13/21 Pages) ATMEL Corporation – Area Array CCD Image Sensor 1024 x 1024 Pixels with Antiblooming

TH7887A
Table 2. Drive Clock Characteristics (Continued)
Value
Parameter
Symbol
Min
Typ
Max
Unit
Reset gate
ΦR
High level
Low level
10
11
12
V
0
0.5
0.8
V
Readout register clocks
High level
Low level
ΦL1, 2
8.5
9
9.5
V
0
0.5
0.8
V
Remarks
Typical input capacitance
10 pF
Φ L1
Φ L2
50 pF
60 pF
75 pF
Maximum readout register
frequency
Image zone to memory zone
transfer frequency
ΦF_H
–
ΦF_V
–
Figure 13. Capacitance Network for Drive Clocks
Φ P2
3.4 nF
Φ P1
2.5 nF
ΦA
3.3 nF
2.5 nF
Φ P3
1.4 nF
ΦP4
20
23
MHz
1.25
1.7
MHz
See Figure 9
See Figure 14
Φ P1
Φ P2
0.7 nF
0.5 nF
VA ^{0.5 nF} _ΦP3
0.7 nF
Φ P4
1.3 nF
ΦA
3.2 nF
Φ P1 ^{4.9 nF} Φ P2
2.2 nF
2.2 nF
4.4 nF
Φ P4
4.4 nF
4.4 nF
Φ P3
3.4 nF
3.9 nF
Φ M1 ^{4.4 nF} Φ M2
3.2 nF
3.2 nF
4.4 nF
Φ M4
4.4 nF
4.4 nF
Φ M3
3.9 nF
13
2146A–IMAGE–05/02