AT80C5112_08 Datasheet, PDF (13/97 Pages) ATMEL Corporation – 8-bit Microcontroller with A/D Converter

Clock Prescaler Register
Clock Control Register
This register is used to reload the clock prescaler of the CPU and peripheral clock.
Table 4. CKRL - Clock Prescaler Register (97h)
7
6
5
4
3
2
1
0
M
Bit
Bit
Number Mnemonic Description
0000 0000b: Division factor equal 512
7: 0
CKRL 1111 1111b: Division factor equal 2
M: Division factor equal 2*(256-M)
Reset value = 1111 1111b
Not bit addressable
This register is used to control the X2 mode of the CPU and peripheral clock.
Table 5. CKCON0 Register (8Fh)
7
6
5
4
3
2
1
0
-
WdX2
PcaX2
SiX2
-
T1X2
T0X2
X2
Bit
Bit
Number Mnemonic Description
7
-
Reserved
Watchdog clock (This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect)
6
WdX2 _{Clear to select 6 clock periods per peripheral clock cycle.}
Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array clock (This control bit is validated when the CPU
clock X2 is set; when X2 is low, this bit has no effect)
5
PcaX2 _{Clear to select 6 clock periods per peripheral clock cycle.}
Set to select 12 clock periods per peripheral clock cycle.
Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the
CPU clock X2 is set; when X2 is low, this bit has no effect)
4
SiX2 _{Clear to select 6 clock periods per peripheral clock cycle.}
Set to select 12 clock periods per peripheral clock cycle.
3
-
Reserved
Timer 1 clock (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect)
2
T1X2 _{Clear to select 6 clock periods per peripheral clock cycle.}
Set to select 12 clock periods per peripheral clock cycle
Timer 0 clock (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect)
1
T0X2 _{Clear to select 6 clock periods per peripheral clock cycle.}
Set to select 12 clock periods per peripheral clock cycle.
12 AT8xC5112
4191C–8051–02/08