ATMEGA406_0607 Datasheet, PDF (128/263 Pages) ATMEL Corporation – 8-bit Microcontroller with 40K Bytes In-System Programmable Flash

to detect that it came from a Power-off situation by monitoring CPU reset flags when it resumes
operation.
22.7
Register Description for Battery Protection
The Battery Protection module operates in a different clock domain than the CPU. Whenever a
new value is written to BPCR, BPDUV, BPOCD, BPSCD, or CPBTR, the value must be synchro-
nized to the Battery Protection clock domain. Subsequent writes to this register should not be
made during this synchronization. Therefore, after writing to one of these registers, the same
register should not be re-written within the next 8 CPU clock periods. Note that each register is
synchronized independently of the others.
22.7.1 BPPLR – Battery Protection Parameter Lock Register
Bit
7
6
5
4
3
2
1
0
(0xF8)
–
–
–
–
–
–
BPPLE
BPPL
BPPLR
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bit 7:2 – Res: Reserved Bits
These bits are reserved bits in the ATmega406 and will always read as zero.
• Bit 1 – BPPLE: Battery Protection Parameter Lock Enable
• Bit 0 – BPPL: Battery Protection Parameter Lock
The Battery Protection parameters set in the Battery Protection Parameter Registers and the
disable function set in the Battery Protection Disable Register can be locked from any further
software updates. Once locked, these registers cannot be accessed until the next hardware
reset. This provides a safe method for protecting these registers from unintentional modification
by software runaway. It is recommended that software sets these registers shortly after reset,
and then protects these registers from any further updates.
To lock these registers, the following algorithm must be followed:
1. In the same operation, write a logic one to BPPLE and BPPL.
2. Within the next four clock cycles, in the same operation. write a logic zero to BPPLE and
a logic one to BPPL.
The Battery Protection Parameter Registers are BPCR, CBPTR, BPOCP, BPSCD and BPDUV.
22.7.2 BPCR – Battery Protection Control Register
Bit
7
6
5
(0xF7)
–
–
–
Read/Write
R
R
R
Initial Value
0
0
0
4
3
2
1
0
–
DUVD
SCD
DCD
CCD
BPCR
R
R/W
R/W
R/W
R/W
0
0
0
0
0
• Bit 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATmega406 and will always read as zero.
• Bit 3 – DUVD: Deep Under-voltage Protection Disable
128 ATmega406
2548E–AVR–07/06