SAM9G46_14 Datasheet, PDF (1258/1286 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

Figure 48-25. SPI Slave Mode - NPCS Timings
SPCK
(CPOL = 0)
SPI₁₄ SPI₆
SPI₁₂
SPI₉
SPCK
(CPOL = 1)
SPI₁₆
MISO
SPI₁₅
SPI₁₃
Table 48-46. UART SPI Timings with 3.3V Peripheral Supply
Symbol
Parameter
Cond
Min
Max
Units
Master Mode
SPI₀
SPCK Period
ns
SPI₁
Input Data Setup Time
17.2
ns
SPI₂
Input Data Hold Time
0
ns
SPI₃
Chip Select Active to Serial Clock
3.5
ns
SPI₄
Output Data Setup Time
0.2
ns
SPI₅
Serial Clock to Chip Select Inactive
-0.3
ns
Slave Mode
SPI₆
SPCK falling to MISO
13.8 ⁽¹⁾
16.9 ⁽¹⁾
ns
SPI₇
MOSI Setup time before SPCK rises
7.5
ns
SPI₈
SPI₉
MOSI Hold time after SPCK rises
SPCK rising to MISO
2.9
4.7 ⁽¹⁾
ns
17.1 ⁽¹⁾
ns
SPI₁₀
MOSI Setup time before SPCK falls
0.4
ns
SPI₁₁
MOSI Hold time after SPCK falls
0
ns
SPI₁₂
NPCS0 setup to SPCK rising
10.3
ns
SPI₁₃
NPCS0 hold after SPCK falling
2.0
ns
SPI₁₄
NPCS0 setup to SPCK falling
10.7
ns
SPI₁₅
NPCS0 hold after SPCK rising
2.0
ns
SPI₁₆
NPCS0 falling to MISO valid
16.0
ns
Notes: 1. For output signals, Min and Max access time must be extracted. The Min access time is the time between the SPCK rising
or falling edge and the signal change. The Max access time is the time between the SPCK rising or falling edge and the
signal stabilization. Figure 48-9 illustrates Min and Max accesses for SPI2. The same applies to SPI5, SPI6, SPI9.
SAM9G46 Series [DATASHEET]
Atmel-11028F-ATARM-SAM9G46-Datasheet_16-Oct-14
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