AT80C51RD2_09 Datasheet, PDF (12/81 Pages) ATMEL Corporation – 80C51 High Performance ROM 8-bit Microcontroller

7. Dual Data Pointer Register
The additional data pointer can be used to speed up code execution and reduce code size.
The dual DPTR structure is a way by which the chip will specify the address of an external data
memory location. There are two 16-bit DPTR registers that address the external memory, and a
single bit called DPS = AUXR1.0 (see Table 7-1) that allows the program code to switch
between them (Refer to Figure 7-1).
Figure 7-1. Use of Dual Pointer
External Data Memory
7
0
DPS
AUXR1(A2H)
DPTR1
DPTR0
DPH(83H) DPL(82H)
Table 7-1. AUXR1 Register
AUXR1- Auxiliary Register 1(0A2h)
7
6
5
4
3
2
-
-
-
-
GF3
0
1
0
-
DPS
Bit
Number
7
6
5
4
3
2
1
0
Bit
Mnemonic Description
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
-
Reserved
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
GF3
0
This bit is a general purpose user flag.
Always cleared⁽¹⁾.
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
DPS
Data Pointer Selection
Cleared to select DPTR0.
Set to select DPTR1.
Reset Value: XXXX XXXX0b
Not bit addressable
Note: 1. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
12 AT80C51RD2
4113D–8051–01/09