ATA5771_10 Datasheet, PDF (116/219 Pages) ATMEL Corporation – Output Power of 8dBm at 315MHz / 7.5dBm at 433.92 MHz / 5.5dBm at 868.3MHz

4.16.11 Register Description
4.16.11.1 TCCR1A – Timer/Counter1 Control Register A
Bit
7
6
5
4
3
0x2F (0x4F)
COM1A1 COM1A0 COM1B1 COM1B0
–
Read/Write
R/W
R/W
R/W
R/W
R
Initial Value
0
0
0
0
0
2
1
0
–
WGM11 WGM10 TCCR1A
R
R/W
R/W
0
0
0
• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B
The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec-
tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of
the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corre-
sponding to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen-
dent of the WGM13:0 bits setting. Table 4-39 shows the COM1x1:0 bit functionality when the
WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 4-39. Compare Output Mode, non-PWM
COM1A1/COM1B1 COM1A0/COM1B0 Description
0
0
Normal port operation, OC1A/OC1B disconnected.
0
1
Toggle OC1A/OC1B on Compare Match.
1
0
Clear OC1A/OC1B on Compare Match (Set output to
low level).
1
1
Set OC1A/OC1B on Compare Match (Set output to
high level).
Table 4-40 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast
PWM mode.
Table 4-40. Compare Output Mode, Fast PWM⁽¹⁾
COM1A1/COM1B1 COM1A0/COM1B0 Description
0
0
Normal port operation, OC1A/OC1B disconnected.
WGM13=0: Normal port operation, OC1A/OC1B
disconnected.
0
1
WGM13=1: Toggle OC1A on Compare Match, OC1B
reserved.
1
0
Clear OC1A/OC1B on Compare Match, set
OC1A/OC1B at BOTTOM (non-inverting mode)
1
1
Set OC1A/OC1B on Compare Match, clear
OC1A/OC1B at BOTTOM (inverting mode)
Note:
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
this case the compare match is ignored, but the set or clear is done at BOTTOM. Section
4.15.7.3 “Fast PWM Mode” on page 83 for more details.
116 Atmel ATA5771/73/74
9137E–RKE–12/10