AT84AD001B Datasheet, PDF (11/60 Pages) ATMEL Corporation – Dual 8-bit 1 Gsps ADC

AT84AD001B
Table 7. Switching Performances
Parameter
Symbol
Min
Typ
Max
Switching Performance and Characteristics - See “Timing Diagrams” on page 12.
Maximum operating clock frequency
F_S
1
Maximum operating clock frequency in BIT and
decimation modes
F_S
(BIT, DEC)
750
Minimum clock frequency (no transparent mode)
10
F_S
Minimum clock frequency (with transparent mode)
1
Minimum clock pulse width [high]
(No transparent mode)
TC1
0.4
0.5
50
Minimum clock pulse width [low]
(No transparent mode)
TC2
0.4
0.5
50
Aperture delay: nominal mode with ISA & FiSDA
TA
1
Aperture uncertainty
Jitter
0.4
Data output delay between input clock and data
TDO
3.8
Data Ready Output Delay
TDR
3
Data Ready Reset to Data Ready
TRDR
2
Data Output Delay with Data Ready
TD2
1/2 Fs
+Tdrda
Data Ready (CLKO) Delay Adjust (140 ps steps)
Tdrda range
-560 to 420
Output skew
50
100
Output rise/fall time for DATA (20% - 80%)
TR/TF
300
350
500
Output rise/fall time for DATA READY (20% - 80%)
TR/TF
300
350
500
Data pipeline delay (nominal mode)
Data pipeline delay (nominal mode) in S/H
transparent mode
TPD
3 (port B)
3.5 (port A, 1:1 DMUX mode)
4 (port A, 1:2 DMUX mode)
2.5 (port B)
3 (port A, 1:1 DMUX mode)
3.5 (port A, 1:2 DMUX mode)
DDRB recommended pulse width
1
Unit
Gsps
Msps
Msps
Ksps
ns
ns
ns
ps (rms)
ns
ns
ns
ps
ps
ps
ps
ps
Clock cycles
ns
11
2153C–BDC–04/04