AT572D740 Datasheet, PDF (11/22 Pages) ATMEL Corporation – DIOPSIS 740 Dual Core DSP

Figure 2. mAgic DSP Block Diagram
AT572D740
VLIW Program Memory
Local Controller and VLIW Decoder
Instruction
Decoder
Condition
Generation
Status
Register
Program
Counter
mAgic – ARM I/F
PARM
PARM
Memory
Memory
Left 512x40 Right 512x40
7001AS–DPS–03/04
Data Register
File
Operator
Block
Multiple
Address
Generation
Unit
Address
Register File
DMA
Controller
Data
Memory
Left 6Kx40
Data
Memory
Right 6Kx40
Buffer Data Buffer Data
Memory Left Memory
2Kx40
Right 2Kx40
External Memory I/F
The operators block, the register file, the address generation unit and the program-
sequencing unit compose the core processor. The Operators Block contains the hard-
ware that performs arithmetical operations. It works on 32-bit integers and IEEE 754
extended precision 40-bit floating-point data.
The Operators Block is composed of four integer/floating point multipliers, an adder, a
subtractor and two add-subtract integer/floating point units; moreover, it has two
shift/logic units, a Min/Max operator and two seed generators for efficient division and
inverse square root computation. The operators block is arranged in order to natively
support complex arithmetic (single cycle complex multiply or multiply and add), fast FFT
(single cycle butterfly computation) and vectorial computations. The peak performance
of mAgic is achieved during single cycle FFT butterfly execution, when mAgic delivers
10 floating-point operations per clock cycle.
mAgic is equipped with two independent address generation units. It is able to generate
up to two pairs of addresses, one to access the left and the right memory for reading
and one to access the left and the right memory for writing. It is also used in the loop
control to test if the end of a loop is reached. The Multiple Address Generation Unit
(MAGU) supports linear addressing with stride, circular addressing and bit reversed
addressing. The address generation unit has 16 registers.
The Program Address Generation Unit is devoted to control the correct Program
Counter generation according to the program flow. It generates addresses for linear
code execution as well as for non-sequential program flow. The Condition Generation
Unit combines the flags generated by the operators to produce complex conditions flags
used to control the program execution. Predicated instruction execution is supported for
different groups of instructions: arithmetical instructions, memory write, immediate load,
or all of them. The Program Address Generation Unit also allows to perform conditioned
and unconditioned branch instructions, loops, call to subroutines and return from sub-
routines.
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