AT572D740 Datasheet, PDF (1/22 Pages) ATMEL Corporation – DIOPSIS 740 Dual Core DSP

Features
• Dual Core System Integrating an ARM7TDMI ARM^ Thumb^ Processor Core and a
mAgic DSP for Audio, Communication and Beam-forming Applications
• High Performance DSP Operating at 100 MHz
– 1 GFLOPS - 1.5 Gops
– 10 Arithmetic Operations per Cycle (4 Multiply, 2 Add/subtract, 1 Add, 1 Subtract
Floating and Fixed Point) Allowing Single Cycle FFT Butterfly
– Native Support for Complex Arithmetic and Vectorial SIMD Operations: One
Complex Multiply with Dual Add/sub per Clock Cycle or Two Real Multiply and Two
Add/sub or Simple Scalar Operations
– 32-bit Integer and IEEE 40-bit Extended Precision Floating Point Numeric Format
– Large Multi-port Data Register File: 512 Registers Organized in Two 4-input 4-
output 256-register Banks
– Orthogonal VLIW Architecture, Code Compression for Code Size Reduction
– Flexible Addressing Capability: 2 Independent Address Generation Units
Operating on a 16 Registers Address Register File Supporting Programmable
Stride, Circular Pointers and Bit Reversal
– 1.7 Mbits of On-chip SRAM:
17 K x 40-bit Data Memory Locations
8 K x 128-bit Program Memory Location, Equivalent to 24K Instructions
– DMA Access to the External Program and Data Memory
– Two Main Operating Modes: Run and System Mode
– Efficient Optimizing Assembler: Allows Easy Exploitation of the Available
Hardware Resources Parallelism
• Utilizes the ARM7TDMI Processor Core with 32 K Byte of Integrated SRAM,
Operating at 50 MHz
– Fully-programmable External Bus Interface (EBI)
Maximum External Address Space of 4 M Bytes
Up to 4 Chip Selects
Software-programmable 8/16-bit External Data Bus
– 8-channel Peripheral Data Controller (PDC)
– 8-level Priority, Individually Maskable Vectored Interrupt Controller
4 External, 20 Internal Interrupt Sources, Including a High-priority, Low-latency
Interrupt Request
– 28 Programmable I/O Lines
– 8-channel 11-bit Programmable Clock Prescaler Feeding the Timer, Watchdog,
USARTs, SPIs
– 3-channel 16-bit Timer/Counter
5 Internal Clock Sources and 3 Configurable Sources (External Source or
Cascaded Timer Configuration)
2 Multi-purpose Output Pins plus 1 Output Dedicated to the ADDA Interface plus
3 Outputs Dedicated to the mAgic DSP
– 2 USARTs
2 Dedicated Peripheral Data Controller (PDC) Channels per USART
1 USART Supporting Full Modem Interface
– 2 Master/Slave SPI Interfaces
2 Dedicated Peripheral Data Controller (PDC) Channels per SPI
8- to 16-bit Programmable Data Length
4 External Slave Chip Selects for each SPI
– Programmable Watchdog Timer
– ADDA (A/D and D/A Converters) Interface Supporting up to 4 Analog to Digital and
4 Digital to Analog, Stereo 24-bit Converters
– IEEE 1149.1 JTAG Boundary Scan on all Active Pins
• Efficient ARM - DSP Interface Based on 1K x 40-bit Dual Ported Shared Memory,
Memory Mapped Register Access, and Interrupt Lines
• 1.8 V Core Operating Voltage, 3.3 V I/O Operating Voltage
• On-chip PLL for 100 Mhz Operation from 25 Mhz Reference Clock
• 352-ball PBGA Package
DIOPSIS 740
Dual Core DSP
AT572D740
Summary
7001AS–DSP–03/04
Note: This is a summary document. A complete document
is not available at this time. For more information, please
contact your local Atmel sales office.