AT25DQ161_09 Datasheet, PDF (11/64 Pages) ATMEL Corporation – 16-Megabit 2.7-volt Minimum SPI Serial Flash Memory with Dual-I/O and Quad-I/O Support

AT25DQ161 [Preliminary]
Figure 7-3. Read Array – 03h Opcode
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36 37 38 39 40
OPCODE
ADDRESS BITS A23-A0
0 0 0 0 0 0 1 1AAAAAA
MSB
MSB
HIGH-IMPEDANCE
AAA
DATA BYTE 1
DDDDDDDDDD
MSB
MSB
7.2 Dual-Output Read Array
The Dual-Output Read Array command is similar to the standard Read Array command and can
be used to sequentially read a continuous stream of data from the device by simply providing the
clock signal once the initial starting address has been specified. Unlike the standard Read Array
command, however, the Dual-Output Read Array command allows two bits of data to be clocked
out of the device on every clock cycle rather than just one.
The Dual-Output Read Array command can be used at any clock frequency up to the maximum
specified by f_RDDO. To perform the Dual-Output Read Array operation, the CS pin must first be
asserted and the opcode of 3Bh must be clocked into the device. After the opcode has been
clocked in, the three address bytes must be clocked in to specify the starting address location of
the first byte to read within the memory array. Following the three address bytes, a single
dummy byte must also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles
will result in data being output on both the I/O₁ and I/O₀ pins. The data is always output with the
MSB of a byte first, and the MSB is always output on the I/O₁ pin. During the first clock cycle, bit
7 of the first data byte will be output on the I/O₁ pin while bit 6 of the same data byte will be out-
put on the I/O₀ pin. During the next clock cycle, bits 5 and 4 of the first data byte will be output on
the I/O₁ and I/O₀ pins, respectively. The sequence continues with each byte of data being output
after every four clock cycles. When the last byte (1FFFFFh) of the memory array has been read,
the device will continue reading back at the beginning of the array (000000h). No delays will be
incurred when wrapping around from the end of the array to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the I/O_1-0 pins into a high-
impedance state. The CS pin can be deasserted at any time and does not require that a full byte
of data be read.
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8671A–DFLASH–07/09