ATR2406 Datasheet, PDF (10/20 Pages) ATMEL Corporation – LOW IF .4 GHZ ISM TRANSCEIVER

RX Register Setting
The are two RX settings possible. For a data rate of 1152 kBit/s an internal clock recov-
ery function is implemented.
Register Setting without Must be used for data rates below 1.152 Mbit.
Clock Recovery
MSB
LSB
Data bits
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2 D1
D0
0
1
X
X
X
X
X
0
RC
MC
SC
Note: X values are not relevant and can be set to 0 or 1.
RX Register Setting with
Internal Clock Recovery
Recommended for 1.152 Mbit data rate.
The output pin of the recovered clock is pin 6. The falling edge of the recovered clock
signal samples the data signal.
MSB
Data bits
D24
D23
D22
D21
D20
1
0
1
0
0
D19
D18 D17 D16
0
0
0
0
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2 D1
D0
0
0
X
X
X
X
X
0
RC
MC
SC
Note: X values are not relevant and can be set to 0 or 1.
PLL Settings
RC, MC and SC bits are controlling the synthesizer frequency according to Table 3,
Table 4 and Table 5.
Formula for calculating the frequency:
TX frequency: f_ANT = 864 kHz × (32 × S_MC + S_SC)
RX frequency: f_ANT = 864 kHz × (32 × S_MC + S_SC + 1)
Table 3. PLL Settings with the Reference Counter Bit D7
RC (Reference Counter)
D7
CLK Reference
0
10.368 MHz
1
13.824 MHz
10 ATR2406 [Preliminary]
4779F–ISM–09/04