AT24C21_03 Datasheet, PDF (10/17 Pages) ATMEL Corporation – 2-wire Serial EEPROM

Write Operations
BYTE WRITE: A write operation requires an 8-bit data word addresses following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8-bit data word. Following
receipt of the 8-bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condi-
tion. At this time the EEPROM enters an internally-timed write cycle , t_WR, to the
nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will
not respond until the write is complete (refer to Figure 5).
It is required that VCLK be held at a high logic level in order to program the device. This
applies to byte write and page write operation. Note that VCLK can go low while the
device is in its self-timed program operation and not affect programming.
PAGE WRITE: The AT24C21 is capable of an 8-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send
a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to seven
more data words. The EEPROM will respond with a zero after each data word received.
The microcontroller must terminate the page write sequence with a stop condition (refer
to Figure 6).
The data word address lower three bits are internally incremented following the receipt
of each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than eight data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten. The address “roll over” during write is from
the last byte of the current page to the first byte of the same page.
It is required that VCLK be held at a high logic level in order to program the device. This
applies to byte write and page write operation. Note that VCLK can go low while the
device is in its self-timed program operation and not affect programming.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero allowing the read or write sequence to continue.
WRITE PROTECTION: When VCLK pin is connected to GND and in the Bidirectional
Mode, the entire memory is protected and becomes ROM only. This protects the device
memory from any inadvertent write operations.
NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins pre-
vent small noise spikes from activating the device. Furthermore, the AT24C21 employs
a low V_CC detector circuit which disables the erase\write logic whenever V_CC falls below
1.5 volts.
10 AT24C21
0405I–SEEPR–7/03