MH1RT_14 Datasheet, PDF (1/19 Pages) ATMEL Corporation – Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC

Features
• Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries
• High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 (nominal)
• System Level Integration Technology Cores on Request
• Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC
• I/O Interfaces:
– 5V Tolerant/Compliant (S) or 3V (R) Matrix Options
– CMOS, LVTTL, LVDS, PCI, USB, etc.
– Output Currents Programmable from 2 to 24 mA, by Step of 2 mA
– Cold Sparing Buffers (2 µA Max. Leakage Current at 3.6V Worst Case Mil Temp.)
• 250 MHz PLL (on request), 220 MHz LVDS and 800 MHz Max. Toggle Frequency at 3.3V
• Deep Submicron CAD Flow
• ESD better than 2000V
• No Single Event Latch-Up below an LET Threshold of 80 MeV/mg/cm²
• SEU Hardened Flip-flops
• Tested Up to a Total Dose of 300 Krad (Si) according to Mil STD 883 Method 1019
• Quality Grades
- QML Q and V with SMD 5962-01B01 and 5962-08B01
- ESCC QML with ESCC 9202 / 076
Description
The MH1RT Gate Array and Embedded Array families from Atmel are fabricated on a
radiation hardened 0.35 micron CMOS process, with up to 4 levels of metal for inter-
connect. This family features arrays with up to 1.6 million routable gates and 596
pads. The high density and high pin count capabilities of the MH1RT family, coupled
with the ability to embed cores or memories on the same silicon, make the MH1RT
series of arrays one of the best choices for System Level Integration.
The MH1RT series is supported by an advanced software environment based on
industry standards linking proprietary and commercial tools. Verilog^®, DFT^®, Synop-
sys^® and Vital are the reference front end tools. The Cadence^® ‘Logic Design Planner’
floor planning associated with timing driven layout provides an efficient back end
cycle.
The MH1RT series comes as a dual use of the MH1 series, adding:
- through process changes, the latch-up susceptibility better than 80 MeV/mg/cm² and
the 300 Krad (Si) radiation level as required by most space programs.
- through cells relayout, an SEU built-in protection allowing to SEU harden only where
it is necessary with respect to function requirements
With a background of 15 years experience, the MH1RT series comes as the Atmel
7th generation of ASIC series designed for radiation hardened applications.
Rad Hard
1.6M Used Gates
0.35 µm CMOS
Sea of Gates/
Embedded Array
MH1RT
4110L–AERO–11/10