IC-LNG_14 Datasheet, PDF (20/30 Pages) IC-Haus GmbH – 16-BIT OPTO ENCODER

iC-LNG 16-BIT OPTO ENCODER ^preliminary
WITH SPI AND SERIAL / PARALLEL OUTPUTS
Rev B1, Page 20/30
SVALID
Code
0
1
Description
Sensor data invalid
Sensor data valid
Table 13: SVALID
CS
SCLK
MOSI
MISO
REQ
OP
OP SV 0-7 SV 8-15 ...
8 cycles
Figure 9: SDAD status
If only one slave is connected, the relevant SVALID bit
is placed at bit position 7 in the SVALID byte.
CS
SCLK
MOSI
MISO
REQ
OP
00000000
OP SV 0 0 0 0 0 0 0 0
8 cycles
SVALID vector
Figure 10: SDAD status (one slave)
REGISTER status/data
The status of the last REGISTER communication or
the last data transmission can be queried using the
REGISTER status/data command. The STATUS byte
contains the information summarized in Table 14.
STATUS
Bit
7
6..4
3
2
1
0
NB
Name
Description of the status
report
ERROR
Opcode invalid. Sensor
data was invalid on
readout
-
Reserved
DISMISS
Address refused
FAIL
Data request has failed
BUSY
Slave is busy with a
request
VALID
DATA is valid
Display logic: 1 = true, 0 = false
Table 14: SPI status information
signals whether an error occurred during the last com-
munication with the SPI interface or not.
The master transmits the opcode REGISTER sta-
tus/data. iC-LNG immediately passes the opcode on
to MISO. iC-LNG then transmits the STATUS byte and
a DATA byte. The DATA byte is not available in iC-LNG
and is thus not defined.
CS
SCLK
MOSI
MISO
OP
OP STATUS DATA
8 cycles
Figure 11: REGISTER status/data
Read REGISTER (cont.)
The master transmits the opcode Read REGISTER
(cont.). Start address ADR, from which point data is
to be read, is transmitted in the 2nd byte. The slave
immediately outputs the opcode and address and then
transmits DATA1. The internal address counter is in-
cremented after each data package.
If an error occurs during register readout (cont.), i.e.
the address is invalid, the requested data was not
valid on data byte clocking, etc., the internal address
counter is incremented no further and the FAIL error
bit is set in the status byte (Table 14).
CS
SCLK
MOSI
MISO
OP ADR
OP ADR DATA1 DATA2 ...
8 cycles
Figure 12: Read REGISTER (cont.)
Write to REGISTER (cont.)
The master transmits the opcode Write to REGISTER
(cont.). Start address ADR, from which point succes-
sive data DATA1-DATAn is to be written, is transmitted
in the 2nd byte. The slave immediately outputs the
opcode, address, and data at MISO. The slave incre-
ments its internal address counter after each DATAn
data package.
All status bits are updated with each register access. If an error occurs during a write to register (cont.), i.e.
The ERROR bit is the exception to the rule; this bit the address is invalid, writing of the last address data