AP89042_15 Datasheet, PDF (15/19 Pages) Aplus Intergrated Circuits – APLUS INTEGRATED CIRCUITS INC

Integrated Circuits Inc.
aP89042
AC CHARACTERISTICS ( T_A = 0 to 70℃, VDD = 3.3V, VSS = 0V, 8KHz sampling )
KEY Trigger Mode
S1~S8,
tKD
tKDD
SBT
COUT
tUP
STOP
tSTPD
tDN
tSTPW
BUSY
tBD
tBH
CPU Parallel Mode
Addr.
S1~S5
tASH
SBT
tSBTW
tASH
Symbol Parameter
Min. Typ. Max.
tKD
Key trigger debounce time
16


tKD
Key trigger debounce time – retrigger 24


tUP
Ramp up time
0 128/Fs −−
tDN
Ramp down time
0
−− 256/Fs
tKDD Key trigger delay after ramp down
−−
0
−−
tSTPD STOP pulse output delay time


256
tSTPW STOP pulse width

64

tBD
BUSY signal output delay time


100
tBH
BUSY signal output hold time

100

tASH Address set-up / hold time
100 

tSBTW SBT stroke pulse width
16


tLEDC LED flash frequency

3

Notes : 1. This parameter is inversely proportional to the sampling frequency.
2.This parameter is proportional to the sampling frequency.
3. Fs is sampling frequency in Hz
Ver5.0
15
Unit Note
ms
1
ms
1
s
3
s
3
ms
µs
ms
1
ns
ns
ns
ms
1
Hz
2
Aug 23, 2010