AP8910A1_15 Datasheet, PDF (11/18 Pages) Aplus Intergrated Circuits – Integrated Circuits Inc

Integrated Circuits Inc.
CPU Parallel Trigger Mode
aP8921A/10A
In this mode, S1 to S4 are set to HIGH or LOW according to the table above and followed by
setting the SBT input pin to HIGH, the corresponding Voice Group will be triggered.
Trigger options defined in Fig. 4, 5, 7 and 8 are valid for this mode.
Fig. 11 CPU Parallel Trigger Mode
Note that SBT pin cannot be used as Single Button Sequential trigger in this mode. In stead, it
acts as a Strobe input to clock-in the data input from S1 to S4 into the chip.
Voice Groups address is determined by the Voice Group Trigger Table. For example:
S1..S4 = 1000 for Voice Group #1
S1..S4 = 0100 for Voice Group #2
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S1..S4= 1100 for Voice Group #5
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S1..S4 = 1110 for Voice Group #9
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S1..S4 = 1101 for Voice Group #12
Ver 5.0
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Aug 23, 2011