CS1630 Datasheet, PDF (38/56 Pages) Cirrus Logic – 2-Channel TRIAC Dimmable LED Driver IC

CS1630/31
6.22 Configuration 17 (Config17) – Address 49
7
DITHER
6
RESYNC
5
4
3
2
1
0
T2CH2GAIN5 T2CH2GAIN4 T2CH2GAIN3 T2CH2GAIN2 T2CH2GAIN1 T2CH2GAIN0
Number
Name
Description
Configures dither on the second stage primary side peak current threshold.
[7]
DITHER
0 = Disable dither
1 = Enable dither
Configures resynchronization of a dual channel second stage design where
the channel synchronization circuit is not directly driven from the SYNC pin. Bit
[6]
RESYNC
RESYNC controls the behavior of bits EXIT_PH[3:0] and DECL_PH[3:0] (see
"Configuration 15 (Config15) – Address 47" on page 37).
0 = Disable phase resynchronization
1 = Enable phase resynchronization
[ 3:0 ]
Sets T2 compensation gain T2_CH2CompGain for channel 2 which is required
when T2 measurement compensation is enabled for flyback designs. The
value is an unsigned integer in the range of 0T2_CH2CompGain<63. Compen-
sated T2 time T2_Compensated used in the second stage charge regulation loop
T2CH2GAIN[5:0] ^{is given by:}
T2_Compensated = T2_Measured – T_{ZCDRi sin gEdge}  T2_CH2CompGain
where,
T2_CH2CompGain is a decimal number the range of 0.0T2_CH2CompGain<4.0.
T2_CH2CompGain = T2CH2GAIN[5:0]  0.0625
6.23 Configuration 18 (Config18) – Address 50
7
LEB3
6
LEB2
5
LEB1
4
LEB0
3
TEB3
2
TEB2
1
TEB1
0
TEB0
Number
[ 7:4 ]
[ 3:0 ]
Name
LEB[3:0]
TEB[3:0]
Description
Configures the leading-edge blanking time T_LEB for the second stage peak
current measurement. The output of the current sense comparator which con-
trols the primary side peak current is ignored for time T_LEB from the rising
edge of the gate drive signal.
T_LEB = LEB[3:0]  2  50ns
Configures the trailing-edge blanking time T_TEB for zero-current detection. The
ZCD comparator output signal used to detect the secondary side inductor
demagnetization is blanked for time T_TEB after the falling edge of the second
stage gate drive signal.
T_TEB = TEB[3:0]  2  50ns
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DS954F2