ADSP-BF542_1 Datasheet, PDF (58/100 Pages) Analog Devices – Embedded Processor

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
External DMA Request Timing
Table 39 and Figure 29 describe the external DMA request tim-
ing operations.
Table 39. External DMA Request Timing
Parameter
Timing Parameters
t_DR
t_DH
t_DMARACT
t_DMARINACT
DMARx Asserted to CLKOUT High Setup
CLKOUT High to DMARx Deasserted Hold Time
DMARx Active Pulse Width
DMARx Inactive Pulse Width
Min
Max
6.0
0.0
1.0 × t_SCLK
1.75 × t_SCLK
Unit
ns
ns
ns
ns
CLKOUT
DMAR0/1
(ACTIVE LOW)
DMAR0/1
(ACTIVE HIGH)
t_DS
t_DH
t_DMARACT
t_DMARINACT
Figure 29. External DMA Request Timing
Rev. C | Page 58 of 100 | February 2010