ADSP-BF542_1 Datasheet, PDF (45/100 Pages) Analog Devices – Embedded Processor

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Table 29. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Parameter
Timing Requirements
t_SDAT
DATA15–0 Setup Before CLKOUT
t_HDAT
DATA15–0 Hold After CLKOUT
t_DANR
ARDY Negated Delay from AMSx Asserted¹
t_HAA
ARDY Asserted Hold After ARE Negated
Switching Characteristics
t_DO
Output Delay After CLKOUT²
t_HO
Output Hold After CLKOUT²
1 _{S = number of programmed setup cycles, RA = number of programmed read access cycles.}
2 _{Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, and ARE.}
Min
Max
Unit
5.0
ns
0.8
ns
(S + RA – 2) × t_SCLK ns
0.0
ns
6.0
ns
0.3
ns
CLKOUT
AMSx
SETUP
2 CYCLES
t_DO
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
HOLD
3 CYCLES
1 CYCLE
t_HO
ABE1–0
ADDR19–1
AOE
ARE
ARDY
DATA 15–0
t_DO
t_DANR
t_HO
t_SDAT
tHAA
t_HDAT
Figure 14. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Rev. C | Page 45 of 100 | February 2010