AAT3601_08 Datasheet, PDF (33/37 Pages) Advanced Analogic Technologies – Total Power Solution for Portable Applications

PRODUCT DATASHEET
AAT3601178
Total Power Solution for Portable Applications
Layout Guidance
Figure 12 is the schematic for the evaluation board. The
evaluation board has extra components for easy evalua-
tion; the actual BOM need for the system is shown in
Table 10. When laying out the PC board, the following
layout guideline should be followed to ensure proper
operation of the AAT3601:
1. The exposed pad EP must be reliably soldered to
PGND/AGND and multilayer GND. The exposed ther-
mal pad should be connected to board ground plane
and pins 17 and 31. The ground plane should include
a large exposed copper pad under the package with
VIAs to all board layers for thermal dissipation.
2. The power traces, including GND traces, the LX
traces and the VIN trace should be kept short, direct
and wide to allow large current flow. The L1 connec-
tion to the LX pins should be as short as possible.
Use several via pads when routing between layers.
3. The input capacitors (C1 and C2) should be con-
nected as close as possible to CHGIN (Pin 28) and
PGND (Pin 31) to get good power filtering.
4. Keep the switching node LX away from the sensitive
OUTBUCK feedback node.
5. The feedback trace for the OUTBUCK pin should be
separate from any power trace and connected as
closely as possible to the load point. Sensing along a
high current load trace will degrade DC load regula-
tion.
6. The output capacitor C4 and L1 should be connected
as close as possible and there should not be any
signal lines under the inductor.
7. The resistance of the trace from the load return to
the PGND (Pin 31) should be kept to a minimum.
This will help to minimize any error in DC regulation
due to differences in the potential of the internal
signal ground and the power ground.
3601.2008.07.1.1
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