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AAT2550 Datasheet, PDF (28/35 Pages) Advanced Analogic Technologies – Total Power Solution for Portable Applications
AAT2550
Total Power Solution for Portable Applications
PTOTAL
=
IOA2
·
(RDS(ON)H
·
VOA
+
RDS(ON)L
·
(VIN
-
VOA)) + IOB2
VIN
·
(RDS(ON)H
·
VOB
+
RDS(ON)L
·
(VIN
-
VOB))
+ (tSW · FS · (IOA + IOB) + 2 · IQ) · VIN + (VADP - VMIN) · ICH + VADP · IOP
=
0.6A2 · (0.58Ω · 2.5V + 0.56Ω · (3.6V - 2.5V)) + 0.2A2 · (0.58Ω · 1.8V + 0.56Ω · (3.6V - 1.8V))
3.6V
+ 2 · (5ns · 1.4MHz · 0.4A + 70µA) · 3.6V = 0.443W
TJ(MAX) = TAMB + θJA · PLOSS
= 85°C + (28°C/W) · 0.443W
= 97°C
Printed Circuit Board Layout
Use the following guidelines to ensure a proper
printed circuit board layout.
1. Step-down converter bypass capacitors (C4
and C5 in Figure 4) must be placed as close as
possible to the step-down converter inputs.
2. The connections from the LXA and LXB pins of
the step-down converters to the output induc-
tors should be kept as short as possible. This
is a switching node, so minimizing the length
will reduce the potential of this noisy trace
interfering with other high impedance noise
sensitive nodes.
3. The feedback trace should be separate from
any power trace and connected as closely as
possible to the load point. Sensing along a high
current load trace will degrade the DC load reg-
ulation. If external feedback resistors are used,
they should be placed as closely as possible to
the FB pin. This prevents noise from being cou-
pled into the high impedance feedback node.
4. The resistance of the trace from the load return
to GND should be kept to a minimum. This min-
imizes any error in DC regulation due to differ-
ences in the potential of the internal signal
ground and the power ground.
5. For good thermal coupling, vias are required
from the pad for the QFN paddle to the ground
plane. Via diameters should be 0.3mm to
0.33mm and positioned on a 1.2mm grid. Avoid
close placement to other heat generating
devices.
6. Minimize the trace impedance from the battery
to the BAT pin. The charger output is not
remotely sensed, so any drop in the output
across the BAT output trace feeding the battery
will add to the error in the EOC battery voltage.
To minimize voltage drops on the PCB, main-
tain an adequate high current carrying trace
width.
28
2550.2006.07.1.0