AAT2603_08 Datasheet, PDF (22/26 Pages) Advanced Analogic Technologies – Total Power Solution for Portable Applications

PRODUCT DATASHEET
AAT2603
Total Power Solution for Portable Applications
Thermal Calculations
There are three types of losses associated with the
AAT2603 total power management solution [two step-
down and four LDO regulators]: switching losses, con-
duction losses, and quiescent current losses. Conduction
losses are associated with the R_DS(ON) characteristics of
the internal power switches/FETs of both of the step-
down regulators and the power loss associated with the
voltage difference across the pass switch/FET of the four
LDO regulators. Switching losses are dominated by the
gate charge of the power output switching devices. At
full load, assuming continuous conduction mode (CCM),
a simplified form of the losses is given by the following
(quiescent and switching losses are ignored, since con-
duction losses are so dominant):
P_DC-DC1 =
I_O12 · (R_DS(ON)H1 · V_OB1 + R_DS(ON)L1 · [V_INB1 - V_OB1])
V_INB1
P_DC-DC2 =
I_O22 · (R_DS(ON)H2 · V_OB2 + R_DS(ON)L2 · [V_INB2 - V_OB2])
V_INB2
P_LDO1 = I_LDO1 · (V_INL12 - V_OL1)
P_LDO2 = I_LDO2 · (V_INL12 - V_OL2)
P_LDO3 = I_LDO3 · (V_INL34 - V_OL3)
P_LDO4 = I_LDO4 · (V_INL34 - V_OL4)
P_TOTAL = P_{DC_DC1} + P_{DC_DC2} + P_LDO1 + P_LDO2 + P_LDO3 + P_LDO4
P_DC-DCX: Power dissipation of the specific DC-DC
regulator
I_OX:
Output current of the specific DC-DC regulator
R_DS(ON)HX: Resistance of the internal high-side switch/FET
R_DS(ON)LX: Resistance of the internal low-side switch/FET
V_OBX: Output voltage of the specific DC-DC regulator
V_INBX: Input voltage of the specific DC-DC regulator
P_LDOX: Power dissipation of the specific LDO regulator
I_LDOX: Output current of the specific LDO regulator
V_INLXX: Input voltage of the specific LDO regulator
V_OLX: Output voltage of the specific LDO regulator
P_TOTAL: Total power dissipation of the AAT2603
Since R_DS(ON) and conduction losses all vary with input
voltage, the dominant losses should be investigated over
the complete input voltage range. Given the total con-
duction losses, the maximum junction temperature
(125°C) can be derived from the θ_JA for the TQFN44-28
package which is 50°C/W.
T_J(MAX) = P_TOTAL · θ_JA + T_A
T_J(MAX): Maximum junction temperature
P_TOTAL: Total conduction losses
Θ_JA: Thermal impedance of the package
T_A:
Ambient temperature
Layout
The suggested PCB layout for the AAT2603 is shown in
Figures 4 and 5. The following guidelines should be used
to help ensure a proper layout.
1. The input capacitors (C1, C2, C7, C13, and C16)
should connect as closely as possible to INB1 (Pin
26), INB2 (Pin 27), AIN (Pin 20), INL12 (Pin 16),
INL34 (Pin 8), and AGND/PGND1/PGND2 (Pins 5,
25, and 27).
2. C3/C18 (step-down regulator output capacitors) and
L1/L2 should be connected as closely as possible.
The connection of L1/L2 to the LX1/LX2 pins should
be as short as possible.
3. The feedback trace or FBXX pin (Pins 3, 6, 10, 14,
18, and 21) should be separate from any power
trace and connect as closely as possible to the load
point. Sensing along a high current load trace will
degrade DC load regulation. If external feedback
resistors are used, they should be placed as closely
as possible to the FBXX pin (Pins 3, 6, 10, 14, 18,
and 21) to minimize the length of the high imped-
ance feedback trace.
4. The resistance of the trace from the load return to
the PGND1/PGND2 (Pins 25 and 28) should be kept
to a minimum. This will help to minimize any error
in DC regulation due to differences in the potential
of the internal signal ground and the power ground.
5. For good thermal coupling, PCB vias are required
from the pad for the TDFN44-28 exposed paddle to
the ground plane.
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2603.2008.10.1.2