AAT2603_08 Datasheet, PDF (19/26 Pages) Advanced Analogic Technologies – Total Power Solution for Portable Applications

PRODUCT DATASHEET
AAT2603
Total Power Solution for Portable Applications
I = _RMS(MAX)
I_O
2
V_{O · 1 -} V_O
The term ^{VIN VIN} appears in both the input voltage rip-
ple and input capacitor RMS current equations and is a
maximum when V_O is twice V_IN. This is why the input
voltage ripple and the input capacitor RMS current ripple
are a maximum at 50% duty cycle.
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the AAT2603 step-
down switching regulators. Low ESR/ESL X7R and X5R
ceramic capacitors are ideal for this function. To mini-
mize stray inductance, the capacitor should be placed as
closely as possible to the IC. This keeps the high fre-
quency content of the input current localized, minimizing
EMI and input voltage ripple.
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the eval-
uation board input voltage pins. The inductance of these
wires, along with the low-ESR ceramic input capacitor,
can create a high Q network that may affect converter
performance. This problem often becomes apparent in
the form of excessive ringing in the output voltage dur-
ing load transients. Errors in the loop phase and gain
measurements can also result.
Since the inductance of a short PCB trace feeding the
input voltage is significantly lower than the power leads
from the bench power supply, most applications do not
exhibit this problem.
In applications where the input power source lead induc-
tance cannot be reduced to a level that does not affect
the converter performance, a high ESR tantalum or alu-
minum electrolytic should be placed in parallel with the
low ESR, ESL bypass ceramic. This dampens the high Q
network and stabilizes the system.
Output Capacitor
The output capacitor limits the output ripple and provides
holdup during large load transitions. A 10μF to 22μF X5R
or X7R ceramic capacitor typically provides sufficient bulk
capacitance to stabilize the output during large load tran-
sitions and has the ESR and ESL characteristics neces-
sary for low output ripple. A 10μF X5R or X7R ceramic
capacitor is required for DC-DC2 and a 22μF X5R or X7R
ceramic capacitor is required for DC-DC1; see Table 3 for
suggested capacitor components.
The output voltage droop due to a load transient is dom-
inated by the capacitance of the ceramic output capacitor.
During a step increase in load current, the ceramic output
capacitor alone supplies the load current until the loop
responds. Within several switching cycles, the loop
responds and the inductor current increases to match the
load current demand. The relationship of the output volt-
age droop during the several switching cycles to the out-
put capacitance can be estimated by:
C_OUT
=
3 · ΔI_LOAD
V_DROOP · F_S
Once the average inductor current increases to the DC
load level, the output voltage recovers. The above equa-
tion establishes a limit on the minimum value for the
output capacitor with respect to load transients.
The internal voltage loop compensation also limits the
minimum output capacitor value to 10μF for DC-DC2 and
22μF for DC-DC1. This is due to its effect on the loop
crossover frequency (bandwidth), phase margin, and
gain margin. Increased output capacitance will reduce
the crossover frequency with greater phase margin.
The maximum output capacitor RMS ripple current is
given by:
I = _RMS(MAX)
1
2·
·
3
V_OUT · (V_IN(MAX) - V_OUT)
L · F_S · V_IN(MAX)
Dissipation due to the RMS current in the ceramic output
capacitor ESR is typically minimal, resulting in less than
a few degrees rise in hot-spot temperature.
Feedback Resistor Selection
Resistors R1 and R2 of Figure 1 program the output to
regulate at a voltage higher than 0.6V. To limit the bias
current required for the external feedback resistor string
while maintaining good noise immunity, the minimum
suggested value for R2 is 59kΩ. Although a larger value
will further reduce quiescent current, it will also increase
the impedance of the feedback node, making it more
sensitive to external noise and interference. Table 42
summarizes the resistor values for various output volt-
ages with R2 set to either 59kΩ for good noise immu-
nity or 221kΩ for reduced no load input current.
2603.2008.10.1.2
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