AAT1149 Datasheet, PDF (15/20 Pages) Advanced Analogic Technologies – 3MHz Fast Transient 400mA Step-Down Converter

Thermal Calculations
There are three types of losses associated with the
AAT1149 step-down converter: switching losses,
conduction losses, and quiescent current losses.
Conduction losses are associated with the R_DS(ON)
characteristics of the power output switching
devices. Switching losses are dominated by the
gate charge of the power output switching devices.
At full load, assuming continuous conduction mode
(CCM), a simplified form of the losses is given by:
P_TOTAL =
I_O2 · (R_DS(ON)H · V_O + R_DS(ON)L · [V_IN - V_O])
V_IN
+ (t_sw · F_S · I_O + I_Q) · V_IN
I_Q is the step-down converter quiescent current.
The term t_sw is used to estimate the full load step-
down converter switching losses.
For the condition where the step-down converter is
in dropout at 100% duty cycle, the total device dis-
sipation reduces to:
P_TOTAL = I_O2 · R_DS(ON)H + I_Q · V_IN
Since R_DS(ON), quiescent current, and switching
losses all vary with input voltage, the total losses
should be investigated over the complete input
voltage range.
Given the total losses, the maximum junction tem-
perature can be derived from the θ_JA for the
SC70JW-8 package which is 160°C/W.
AAT1149
3MHz Fast Transient
400mA Step-Down Converter
Layout
The suggested PCB layout for the AAT1149 is
shown in Figures 1, 2, and 3. The following guide-
lines should be used to help ensure a proper layout.
1. The input capacitor (C2) should connect as close-
ly as possible to IN (Pin 3) and PGND (Pins 6-8).
2. C1 and L1 should be connected as closely as
possible. The connection of L1 to the LX pin
should be as short as possible.
3. The feedback trace or FB pin (Pin 2) should be
separate from any power trace and connect as
closely as possible to the load point. Sensing
along a high-current load trace will degrade DC
load regulation. If external feedback resistors
are used, they should be placed as closely as
possible to the FB pin (Pin 2) to minimize the
length of the high impedance feedback trace.
4. The resistance of the trace from the load return
to the PGND (Pins 6-8) should be kept to a
minimum. This will help to minimize any error in
DC regulation due to differences in the poten-
tial of the internal signal ground and the power
ground.
A high density, small footprint layout can be
achieved using an inexpensive, miniature, non-
shielded, high DCR inductor, as shown in Figure 5.
T_J(MAX) = P_TOTAL · Θ_JA + T_AMB
Figure 5: Minimum Footprint Evaluation Board
Using 2.0x1.25x1.0mm Inductor.
1149.2006.11.1.0
15