AAT2153 Datasheet, PDF (14/17 Pages) Advanced Analogic Technologies – 2.5A Low Noise Step-Down Converter

SwitchReg^TM
Thermal Calculations
There are three types of losses associated with the
AAT2153 step-down converter: switching losses, conduc-
tion losses, and quiescent current losses. Conduction
losses are associated with the R_DS(ON) characteristics of the
power output switching devices. Switching losses are
dominated by the gate charge of the power output switch-
ing devices. At full load, assuming continuous conduction
mode (CCM), a simplified form of the losses is given by:
P_TOTAL
=
I_O2
·
(R_DS(ON)H
·
V_O
+ R_DS(ON)L
V_IN
·
[V_IN
-
V_O])
+ (t_sw · F_S · I_O + I_Q) · V_IN
I_Q is the step-down converter quiescent current. The
term t_sw is used to estimate the full load step-down con-
verter switching losses.
For the condition where the step-down converter is in
dropout at 100% duty cycle, the total device dissipation
reduces to:
P_TOTAL
=
I_O2
·
(R_DS(ON)H
·
V_O
+ R_DS(ON)L
V_IN
·
[V_IN
-
V_O])
+ (t_sw · F_S · I_O + I_Q) · V_IN
PRODUCT DATASHEET
AAT2153
2.5A Low Noise Step-Down Converter
Since R_DS(ON), quiescent current, and switching losses all
vary with input voltage, the total losses should be inves-
tigated over the complete input voltage range.
Given the total losses, the maximum junction tempera-
ture can be derived from the θ_JA for the QFN33-16 pack-
age, which is 50°C/W.
T_J(MAX) = P_TOTAL · Θ_JA + T_AMB
Layout
The suggested PCB layout for the AAT2153 is shown in
Figures 3 and 4. The following guidelines should be used
to help ensure a proper layout.
1. The input capacitor (C1) should connect as closely as
possible to VP and PGND.
2. C2 and L1 should be connected as closely as possi-
ble. The connection of L1 to the LX pin should be as
short as possible.
3. The feedback trace or FB pin should be separate
from any power trace and connect as closely as pos-
sible to the load point. Sensing along a high-current
load trace will degrade DC load regulation.
4. The resistance of the trace from the load return to
PGND should be kept to a minimum. This will help to
minimize any error in DC regulation due to differ-
ences in the potential of the internal signal ground
and the power ground.
5. Connect unused signal pins to ground to avoid
unwanted noise coupling.
Figure 3: AAT2153 Evaluation Board
Top Side Layout.
Figure 4: AAT2153 Evaluation Board
Bottom Side Layout.
14
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2153.2008.09.1.0