AAT2153 Datasheet, PDF (12/17 Pages) Advanced Analogic Technologies – 2.5A Low Noise Step-Down Converter

SwitchReg^TM
Component Selection
Inductor Selection
The step-down converter uses peak current mode con-
trol with slope compensation to maintain stability for
duty cycles greater than 50%. The output inductor value
must be selected so the inductor current down slope
meets the internal slope compensation requirements.
The inductor should be set equal to the output voltage
numeric value in μH. This guarantees that there is suf-
ficient internal slope compensation.
Manufacturer’s specifications list both the inductor DC
current rating, which is a thermal limitation, and the
peak current rating, which is determined by the satura-
tion characteristics. The inductor should not show any
appreciable saturation under normal load conditions.
Some inductors may meet the peak and average current
ratings yet result in excessive losses due to a high DCR.
Always consider the losses associated with the DCR and
its effect on the total converter efficiency when selecting
an inductor.
The 3.3μH CDRH4D28 series Sumida inductor has a
49.2mΩ worst case DCR and a 1.57A DC current rating.
At full 2.5A load, the inductor DC loss is 97mW which
gives less than 1.5% loss in efficiency for a 2.5A, 3.3V
output.
Input Capacitor
Select a 10μF to 22μF X7R or X5R ceramic capacitor for
the input. To estimate the required input capacitor size,
determine the acceptable input ripple level (V_PP) and solve
for C. The calculated value varies with input voltage and
is a maximum when V_IN is double the output voltage.
C_IN =
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
⎛ V_PP
⎝ I_O
- ESR^⎞⎠ · F_S
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
=
1
4
for
V_IN
=
2
·
V_O
C_IN(MIN) = _{⎛ VPP}
⎝ I_O
1
- ESR^⎞⎠ · 4 · F_S
Always examine the ceramic capacitor DC voltage coef-
ficient characteristics when selecting the proper value.
For example, the capacitance of a 10μF, 6.3V, X5R ceram-
PRODUCT DATASHEET
AAT2153
2.5A Low Noise Step-Down Converter
ic capacitor with 5.0V DC applied is actually about 6μF.
Some examples of DC bias voltage versus capacitance for
different package sizes are shown in Figure 2.
25.0E+6
20.0E+6
15.0E+6
10.0E+6
5.0E+6
1206 Package
0805 Package
000.0E+0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
DC Bias Voltage (V)
Figure 2: Capacitance vs. DC Bias Voltage for
Different Package Sizes.
The maximum input capacitor RMS current is:
I_RMS = I_O ·
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
The input capacitor RMS ripple current varies with the
input and output voltage and will always be less than or
equal to half of the total DC load current.
V_O
V_IN
· ^⎛⎝1 -
V_O ⎞
V_IN ⎠
=
D · (1 - D) =
0.5²
=
1
2
for V_IN = 2 · V_O
I = _RMS(MAX)
I_O
2
The
term
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
appears
in
both
the
input
voltage
ripple and input capacitor RMS current equations and is
a maximum when V_O is twice V_IN. This is why the input
voltage ripple and the input capacitor RMS current ripple
are a maximum at 50% duty cycle.
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the AAT2153. Low
ESR/ESL X7R and X5R ceramic capacitors are ideal for
this function. To minimize stray inductance, the capaci-
tor should be placed as closely as possible to the IC. This
keeps the high frequency content of the input current
localized, minimizing EMI and input voltage ripple.
The proper placement of the input capacitor (C1) can be
seen in the evaluation board layout in the Layout section
of this datasheet (see Figure 3).
12
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2153.2008.09.1.0