AAT2514 Datasheet, PDF (13/16 Pages) Advanced Analogic Technologies – Dual Channel 600mA Step-Down Converter

AAT2514
Dual Channel 600mA Step-Down Converter
Manufacturer
Murata
Murata
Murata
Part Number
GRM219R60J106KE19
GRM21BR60J226ME39
GRM1551X1E220JZ01B
Value
10µF
22µF
22pF
Voltage (V)
6.3
6.3
25
Temp. Co.
X5R
X5R
JIS
Table 3: Typical Surface Mount Capacitors.
Case
0805
0805
0402
Thermal Calculations
There are three types of losses associated with the
AAT2514 step-down converter: switching losses,
conduction losses, and quiescent current losses.
Conduction losses are associated with the R_DS(ON)
characteristics of the power output switching
devices. Switching losses are dominated by the gate
charge of the power output switching devices. At full
load, assuming continuous conduction mode(CCM),
a simplified form of the losses is given by:
P_TOTAL
=
I_O2
·
(R_DSON(HS)
·
V_O
+ R_DSON(LS)
V_IN
·
[V_IN
-
V_O])
+ (t_sw · F · I_O + I_Q) · V_IN
I_Q is the step-down converter quiescent current.
The term t_sw is used to estimate the full load step-
down converter switching losses.
For the condition where the step-down converter is
in dropout at 100% duty cycle, the total device dis-
sipation reduces to:
P_TOTAL = I_O2 · R_DSON(HS) + I_Q · V_IN
Since R_DS(ON), quiescent current, and switching loss-
es all vary with input voltage, the total losses should
be investigated over the complete input voltage
range. Given the total losses, the maximum junction
temperature can be derived from the θ_JA for the
MSOP-10 or DFN-10 packages, which is 45°C/W.
T_J(MAX) = P_TOTAL · Θ_JA + T_AMB
Layout Guidance
Figure 1 is the schematic for a typical application.
When laying out the PC board, the following layout
guidelines should be followed to ensure proper
operation of the AAT2514:
1. Exposed pad must be reliably soldered to GND.
The exposed thermal pad should be connected to
the board ground plane and GND. The ground
plane should include a large exposed copper pad
under the package for thermal dissipation.
2. The power traces, including the GND trace, the
LX1/LX2 traces, and the VIN trace should be
kept short, direct and wide to allow large current
flow. The L1/2 connection to the LX1/2 pins
should be as short as possible. Use several VIA
pads when routing between layers.
3. The input capacitor (C1) should connect as
closely as possible to IN and GND to get good
power filtering.
4. Keep the switching nodes, LX1/LX2, away from
the sensitive FB1/FB2 nodes.
5. The feedback traces or FB pins should be sepa-
rate from any power trace and connected as
closely as possible to the load point. Sensing
along a high-current load trace will degrade DC
load regulation. The feedback resistors should
be placed as close as possible to the FB pins to
minimize the length of the high impedance feed-
back trace.
6. The output capacitors C2/C3 and L1/L2 should
be connected as close as possible and there
should not be any signal lines under the inductor.
7. The resistance of the trace from the load return
to GND should be kept to a minimum. This will
help to minimize any error in DC regulation due
to differences in the potential of the internal sig-
nal ground and the power ground.
Figure 2 shows an example of a layout with 4 lay-
ers. The 2nd and 3rd layers are Internal GND
Plane.
2514.2007.06.1.0
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