AAT1145_08 Datasheet, PDF (13/17 Pages) Advanced Analogic Technologies – 1.5A Step-Down Converter

SwitchReg^TM
In conclusion, in order to meet the requirement of out-
put voltage ripple small and regulation loop stability,
ceramic capacitors with X5R or X7R dielectrics are rec-
ommended due to their low ESR and high ripple current
ratings. The output ripple V_OUT is determined by:
ΔV_OUT ≤
V_OUT · (V_IN - V_OUT)
V_IN · f_OSC · L
·
⎛⎝_{ESR +}
1
⎞
8 · f_OSC · C_OUT ^⎠
A 22μF ceramic capacitor can satisfy most applications.
Thermal Calculations
There are three types of losses associated with the
AAT1145 step-down converter: switching losses, con-
duction losses, and quiescent current losses. Conduction
losses are associated with the R_DS(ON) characteristics of
the power output switching devices. Switching losses are
dominated by the gate charge of the power output
switching devices. At full load, assuming continuous con-
duction mode (CCM), a simplified form of the losses is
given by:
P_TOTAL
=
I_O2
·
(R_DSON(HS)
·
V_O
+ R_DSON(LS)
V_IN
·
[V_IN
-
V_O])
+ (t_sw · F · I_O + I_Q) · V_IN
I_Q is the step-down converter quiescent current. The
term tsw is used to estimate the full load step-down
converter switching losses.
For the condition where the step-down converter is in
dropout at 100% duty cycle, the total device dissipation
reduces to:
P_TOTAL = I_O2 · R_DSON(HS) + I_Q · V_IN
Since R_DS(ON), quiescent current, and switching losses all
vary with input voltage, the total losses should be inves-
tigated over the complete input voltage range. Given the
total losses, the maximum junction temperature can be
derived from the θ_JA for the DFN-10 package which is
45°C/W.
T_J(MAX) = P_TOTAL · Θ_JA + T_AMB
PRODUCT DATASHEET
AAT1145
1.5A Step-Down Converter
Layout Guidance
When laying out the PC board, the following layout
guideline should be followed to ensure proper operation
of the AAT1145:
1. The exposed pad (EP) must be reliably soldered to
the GND plane. A PGND pad below EP is strongly
recommended.
2. The power traces, including the GND trace, the LX
trace and the IN trace should be kept short, direct
and wide to allow large current flow. The L1 connec-
tion to the LX pins should be as short as possible.
Use several VIA pads when routing between layers.
3. The input capacitor (C1) should connect as closely as
possible to IN (Pin 2) and AGND (Pins 4 and 6) to get
good power filtering.
4. Keep the switching node, LX (Pins 7 and 8), away
from the sensitive FB/OUT node.
5. The feedback trace or OUT pin (Pin 2) should be
separate from any power trace and connect as close-
ly as possible to the load point. Sensing along a
high-current load trace will degrade DC load regula-
tion. If external feedback resistors are used, they
should be placed as closely as possible to the FB pin
(Pin 5) to minimize the length of the high impedance
feedback trace.
6. The output capacitor C2 and L1 should be connected
as closely as possible. The connection of L1 to the LX
pin should be as short as possible and there should
not be any signal lines under the inductor.
7. The resistance of the trace from the load return to
PGND should be kept to a minimum. This will help to
minimize any error in DC regulation due to differ-
ences in the potential of the internal signal ground
and the power ground.
Figures 4 and 5 show an example of a layout with 2
layers.
1145.2008.01.1.2
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