AAT4282A Datasheet, PDF (11/14 Pages) Advanced Analogic Technologies – Dual Slew Rate Controlled Load Switch

AAT4282A
Dual Slew Rate Controlled Load Switch
High Peak Output Current Applications
Some applications require the load switch to oper-
ate at a continuous nominal current level with short
duration, high-current peaks. Refer to the I_DM spec-
ification in the Absolute Maximum Ratings table to
ensure the AAT4282A’s maximum pulsed current
rating is not exceeded. The duty cycle for both out-
put current levels must be taken into account. To do
so, first calculate the power dissipation at the nom-
inal continuous current level, and then add the
additional power dissipation due to the short dura-
tion, high-current peak scaled by the duty factor.
For example, a 4V system using an AAT4282A
which has channel A operates at a continuous 1A
load current level, and channel B operates at a
continuous 100mA load current level and has short
3A current peaks, as in a GSM application. The
current peak occurs for 576μs out of a 4.61ms peri-
od. First, the current duty cycle is calculated:
⎛ x ⎞ ⎛ 576μs ⎞
% Peak Duty Cycle = _{⎝ 100âŽ}  = _{⎝ 4.61msâŽ} 
% Peak Duty Cycle = 12.5%
The load current is 100mA for 87.5% of the 4.61ms
period and 3A for 12.5% of the period. Since the
Electrical Characteristics do not report R_DS(MAX) for
4V operation, it must be approximated by consult-
ing the chart of R_DS(ON) vs. V_IN. The R_DS reported
for 5V at 100mA and 3A can be scaled by the ratio
seen in the chart to derive the R_DS for 4V V_IN at
25°C: 130mΩ · 63mΩ /60mΩ = 136.5mΩ . De-
rated for temperature: 136.5mΩ · (1 + 0.002800 ·
(125°C - 25°C)) = 174.7mΩ.
For channel A, the power dissipation for a continu-
ous 1A load is calculated as follows:
P_D(CHA) = I_OUT² · R_DS = (1A)² · 174.7mΩ = 174.7mW
For channel B, the power dissipation for 100mA
load is calculated as follows:
P_D(MAX) = I_OUT² · R_DS
P_D(100mA) = (100mA)² · 174.7mΩ
P_D(100mA) = 1.75mW
P_D(87.5%D/C) = %DC · P_D(100mA)
P_D(87.5%D/C) = 0.875 · 1.75mW
P_D(87.5%D/C) = 1.53mW
The power dissipation for 100mA load at 87.5%
duty cycle is 1.53mW. Now the power dissipation
for the remaining 12.5% of the duty cycle at 3A is
calculated:
P_D(MAX) = I_OUT² · R_DS
P_D(3A) = (3A)² · 174.7mΩ
P_D(3A) = 1572mW
P_D(12.5%D/C) = %DC · P_D(3A)
P_D(12.5%D/C) = 0.125 · 1572mW
P_D(12.5%D/C) = 196.7mW
Finally, the total power dissipation for channels A
and B is determined as follows:
P_D(total) = P_D(CHA) + P_D(100mA) + P_D(3A)
P_D(total) = 174.7mW + 1.53mW + 196.7mW
P_D(total) = 373mW
The maximum power dissipation for the AAT4282A
operating at an ambient temperature of 85°C is
373mW. The device in this example will have a
total power dissipation of 571mW. This is well with-
in the thermal limits for safe operation of the
device; in fact, at 85°C, the AAT4282A will handle
a 3A pulse for up to 25% duty cycle. At lower ambi-
ent temperatures, the duty cycle can be further
increased.
Printed Circuit Board Layout
Recommendations
For proper thermal management, and to take
advantage of the low R_DS(ON) of the AAT4282A, a
few circuit board layout rules should be followed:
V_IN and V_OUT should be routed using wider than
normal traces, and GND should be connected to a
ground plane. For best performance, C_IN and C_OUT
should be placed close to the package pins.
4282A.2007.09.1.1
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