ARA2000_11 Datasheet, PDF (12/21 Pages) ANADIGICS, Inc – Address-Programmable Reverse Amplifier with Step Attenuator

ARA2000
LOGIC PROGRAMMING
Programming Instructions
The programming word is set through a 16 bit shift
register via the data, clock and enable lines. The
data is entered in order with the most significant bit
(MSB) first and the least significant bit (LSB) last. The
enable line must be low for the duration of the data
entry, then set high to latch the shift register. The
rising edge of the clock pulse shifts each data value
into the register.
dAtA Bit
Value
Table 6: Programming Word
d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
P7 P6 P5 P4 P3 P2 P1 P0 0 0 0 1 C1 C0 1 1
Table 7: Data Description
VAlue
function
( 1 = on, 0 = bypass)
P7
N/A
P6
N/A
P5
32 dB Attenuator Bit
P4
16 dB Attenuator Bit
P3
8 dB Attenuator Bit
P2
4 dB Attenuator Bit
P1
2 dB Attenuator Bit
P0
1 dB Attenuator Bit
Table 8: Device Address
loGic leVel input to
AddRess deVice
c1
c0
pin 16 (c1)
pin 15 (c0)
0
0
0
0
1
0
1
0
0
1
0
1
1
1
1
1
The device is selected when the logic inputs at pins
16 and 15 match the values of data bits C1 and C0,
respectively.
12
Data Sheet - Rev 2.3
04/2011