IAQ-CORE Datasheet, PDF (5/22 Pages) ams AG – The iAQ-Core sensor module is used to measure VOC levels

iAQ-Core − Detailed Description
Detailed Description
Figure 8:
Interface Description
Description
Pull-up resistors
Clock speed
Clock stretching
Figure 9:
Address Byte for the iAQ-Core
Description
Bit
7
6
Data
1
0
I²C Interface Description
Physical Interface
The physical interface is two-wire open drain SCL (clock) and
SDA (data).
Value
External pull-up resistor required
100kHz
Bus master clock stretching support is required
Clock Stretching
Clock stretching pauses a transaction by holding the clock line
low. The transaction cannot continue until the line is released
to high again. Although the module could send the bytes of
data at a fast rate, it could happen that the module is busy at
the request time. It can then hold the clock line low after
reception and acknowledgement of a byte to force the master
into a wait state until the iAQ-Core module is ready for the next
byte transfer in a type of handshake procedure. (See official I²C
specification and user manual UM10204,
http://www.nxp.com/documents/user_manual/UM10204.pdf )
Address
Standard 7 bit I²C address for iAQ-Core is decimal 90 or
hexadecimal 0x5A. The addressing byte includes the
read/write bit at the lowest significant bit. The communication
with the iAQ-Core starts with 0xB5 for reading data.
Note(s): Please avoid addressing the iAQ-Core with write bit.
This could cause a loss of communication relevant information
on modules side and the iAQ-Core is no longer contactable.
Address
R/W
5
4
3
2
1
0
1
1
0
1
0
1
ams Datasheet
[v1-00] 2015-Apr-30
Page 5
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