AS3953A Datasheet, PDF (25/42 Pages) ams AG – High Speed Passive Tag Interface

AS3953A
Datasheet - Application Information
EEPROM Read. In order to read data from EEPROM first a mode byte is sent, followed by the word address byte (MSB first). Then one or
more words of data with address auto incrementing (packets of 4 bytes) are transferred to MISO output, always from the MSB to the LSB. MOSI
is sampled at the falling edge of SCLK; data to be read from the AS3953A EEPROM is driven to MISO pin on rising edge of SCLK and is
sampled by the master at the falling edge of SCLK. In case the word on defined address does not exist all ‘0’ data is sent to MISO.
Please note that SCLK frequency should not exceed 1MHz during EEPROM Read (limited by EEPROM read access time).
Figure 10. Reading of EEPROM Page
/SS
SCLK
MOSI
MISO
WWWWW W W
X 0 11 1 1 1 11 AAAAAAAx
X
65432 1 0
X
1µs min
BBBBB B BB BB
33222 2 22 22
10987 6 54 32
MSB Byte from
Address
<WA6-WA0>
X
BBBBBBBBBB
9876543210
X
LSB Byte from
Address
<WA6-WA0>
8.1.4 Loading Transmitting Data into FIFO
Loading the transmitting data into the FIFO is similar to writing data into an addressable registers. Difference is that in case of loading more bytes
all bytes go to the FIFO. The command mode code 10 indicates FIFO operations. In case of loading transmitting data into FIFO all bits <C5 –
C0> are set to ‘0’. Then a bit-stream, the data to be sent (1 to 32 bytes), can be transferred.
Figure 11 shows how to load the Transmitting data into the FIFO.
Figure 11. Loading of FIFO
/SS
SCLK
MOSI
X1
0
0
0
0
10 pattern
indicates FIFO
mode
SCLK rising
edge Data is
transfered
from µC
0
0
0
SCLK falling
edge Data is
sampled
Start of
payload Data
1 to 32
bytes
X
/SS rising edge
signals end of
COMMAND Mode
8.1.5 Reading Received Data from FIFO
Reading received data from the FIFO is similar to reading data from an addressable registers. Difference is that in case of reading more bytes
they all come from the FIFO. The command mode code 10 indicates FIFO operations. In case of reading the received data from the FIFO all bits
<C5 – C0> are set to ‘1’. On the following SCLK rising edges the data from FIFO appears as in case of read data from addressable registers. In
case the command is terminated by putting /SS high before a packet of 8 bits composing one byte is read that particular byte is considered read.
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