AS3661 Datasheet, PDF (24/87 Pages) ams AG – Programmable 9-channel LED Dr iver

AS3661
Datasheet - Detailed Description
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold
times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge
bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to
enable the master to generate the STOP condition.
Figure 25. Data Transfer on I²C Serial Bus
lid ^SDA
ill ^va _SCL
G _{st START}
CONDITION
MSB
SLAVE
ADDRESS
1
2
6
R/W
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM
RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM
RECEIVER
7
8
9
1
2 3-8 8
9
ACK
REPEATED IF
MORE BYTES ARE
TRANSFERRED
STOP CONDITION
OR REPEATED
START CONDITION
s ^{A nt} _{Depending upon the state of the R/W bit, two types of data transfer are possible:}
e _{1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the}
m ^{t slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received}
byte. Data is transferred with the most significant bit (MSB) first.
a n 2. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave
address). The slave then returns an acknowledge bit, followed by the slave transmitting a number of data
o _{bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the}
last received byte, a “not acknowledge” is returned. The master device generates all of the serial clock pulses
c _{and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START}
condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not
l _{released. Data is transferred with the most significant bit (MSB) first.}
The AS3661 can operate in the following two modes:
a _{1. Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each}
ic ^{byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the begin-}
ning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave
address and direction bit (see Figure 26). The slave address byte is the first byte received after the master
n generates the START condition. The slave address byte contains the 7-bit AS3661 address, which is
0110010², followed by the direction bit (R/W), which, for a write, is 0.³ After receiving and decoding the slave
h _{address byte the device outputs an acknowledge on the SDA line. After the AS3661 acknowledges the slave}
address + write bit, the master transmits a register address to the AS3661. This sets the register pointer on the
c_{AS3661. The master may then transmit zero or more bytes of data (if more than one data byte is written see}
Te^{also Blockwrite/read boundaries on page 24), with the AS3661 acknowledging each byte received. The}
2. ’XXX’ depends on the external connection of ASEL0 and ASEL1; see Chip Address Configuration on page
22
3. The address for writing to the AS3661 is 8Xh = 01100100b - see Table 5
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