TSL1401CCS Datasheet, PDF (17/29 Pages) ams AG – Enables High-Resolution Edge Detection

TSL1401CCS − Application Information
window is active is to lower the output voltage level to prevent
saturation. However, the integration time must still be greater
than or equal to the minimum integration period.
If the light intensity produces an output below desired signal
levels, the output voltage level can be increased by increasing
the integration period provided that the maximum integration
time is not exceeded. The maximum integration time is limited
by the length of time the integrating capacitors on the pixels
can hold their accumulated charge. The maximum integration
time should not exceed 100ms for accurate measurements.
It should be noted that the data from the light sampled during
one integration period is made available on the analog output
during the next integration period and is clocked out
sequentially at a rate of one pixel per clock period. In other
words, at any given time, two groups of data are being handled
by the linear array: the previous measured light data is clocked
out as the next light sample is being integrated.
Although the linear array is capable of running over a wide
range of operating frequencies up to a maximum of 8MHz, the
speed of the A/D converter used in the application is likely to
be the limiter for the maximum clock frequency. The voltage
output is available for the whole period of the clock, so the
setup and hold times required for the analog-to-digital
conversion must be less than the clock period.
ams Datasheet
[v1-00] 2016-Jan-18
Page 17
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